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TMS320F28375D: EMIF memory

Rob Barton
Expert 2220 points
Part Number: TMS320F28375D

In the SPRT720 document section 3 it shows the EMIF-1 memory space as 2Mx16, but in the EMIF section 25 of spruhm8f it shows 512MBit part...  now the comment just before the chart says for devices that support the 16 bit interface...

So to be clear:

for the 28375D, if I look at the memory map it shows 0x100000 for EMIF-1 (2Mx16),

If I put a 512MBit x16 x4  part on there, that should be 8Mx16, but the address space only shows 2Mx16

What is the maximum memory that can be added to the 23875D EMIF1 x16 interface?

a 128MBit SDRAM?  32MBit SDRAM?

  • 0
    TI__Guru** 115271 points

    Hi Rob,

    but in the EMIF section 25 of spruhm8f it shows 512MBit part... 

    Which section in TRM (table number or figure number) shows 512MBit part? Please note that EMIF supports SDRAM and ASRAM interface so maximum memory space will depends based on which interface you are using.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2220 points
    section 25.3.5.2 in spruhm8f
    section 3 memory in sprt720 shows the 2Mx16 limit memory map for the 28375D
  • 0 in reply to Rob Barton
    TI__Guru** 115271 points

    Rob,

    That is for SDRAM interface and what you are referring in sprt720 is for ASRAM interface. Please device manual  for full memory map (Table 6-4. EMIF Chip Select Memory Map).

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2220 points
    Okay, so in the device manual link it shows 256Mx16 address space for the 28375D, so we could add a maximum of 4GBits SDRAM correct?

    Its not clear to me how you differentiate between SDRAM and ASRAM. I'm happy to use either document, but even the memory maps differ between the documents.

    Can you point me to where this is better outlined? Its not clear where the memory SDRAM or SRAM will appear, and what the maximums are for the 28375D part.

    Thanks.
  • 0 in reply to Rob Barton
    TI__Guru** 115271 points

    Rob,

    Chip select CS0 is for SDRAM and CS2/CS3/CS4 are for ASRAM. These details are provided in section "5.7.9 External Memory Interface (EMIF)" of device manual (link I provided).

    On maximum memory size, we have address space available but finding SDRAM device of that size may be difficult.

    Regards,

    Vivek Singh

  • 0 in reply to Rob Barton
    Expert 2220 points

    One more related question, where in the documentation do you discuss how to get burst access to the SDRAM memory?

    For example, If I wrote a simple assembler loop that moves a block of memory, say 8 consecutive words.... I might do something using the rpt or rptb command, and then have a series of MOV instructions to read from memory to a register, then store that register to another memory location (say inside the part)

    However I believe this will generate a series of single SDRAM reads moving one 16 bit word at a time correct?

    Are thre specific commands that indicate that it should do a burst read/write to SDRAM?

    Or is the only way to benefit from the burst reads/writes by using the DMA? I assume when the DMA requests a block of data it will translate that to the appropriate SDRAM burst read/write?

    Since our application is timing critical, processor speed limited, I need to be sure I understand when it will choose to use the burst cycles so I can accurately determine how fast the code (data) will run (or move data back and forth).

    asked another way, how do I specify or stimulate the EMIF to generate a burst read/write in my coding when accessing memory?  (at assembly level)
     
    Thanks.

  • 0 in reply to Rob Barton
    TI__Guru** 115271 points

    Rob,

    rpt/rptb is not supported for this address range. Also DMA does not do back-2-back read or write access (it's load and store operation) so burst access can not be generated for SDRAM.

    Please refer this app note also for more information on accessing SDRAM.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2220 points

    So you mean because the DMA has a read the data, then write the data approach (figure 4-5) of section 4, then this results (assuming I'm copying memory from CPU to SDRAM a read of internal ram then a write to SDRAM, thus no burst write.

    If the bus speed of the external ram is say 100MHz do we extend the timing diagram in figure 4-5 to account for the slower output bus relative to the SYSCLK?

    Is there 'any way' for the processor to generate a burst read/write?  So if we don't use the DMA, is there any method of achieving a burst read and write from this part, or are all external reads and writes therough the EMIF interface a a single 16/32 bit read/write.

    Thanks.

  • 0 in reply to Rob Barton
    Expert 2220 points

    Section 25.3.5.10 shows a burst SDRAM write cycle, so the question amounts to how to in software stimulate the EMIF1 to generate such a cycle?  ie: how do I point to the block of data in software, and say, here is the 8 words (in this example) that I want you to put a burst write onto the EMIF1 SDRAM bus?  Is this possible?

  • 0 in reply to Rob Barton
    TI__Guru** 115271 points

    Hi Rob,

    Burst is not supported on SDRAM. SDRAM waveform need to be updated. We are aware of this issue and it will be updated in next release.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 2220 points
    Okay, thanks, so it's a documentation error.

    Just wanted to be certain. So we are constrained to individual Read and write cycles.

    Also, when reading the documentation I wasn't clear on when looking at things like the DMA (figure 4-5) how to translate sysclk to the bus speed clock... ie: in figure 4-5 it shows the dma takes 4 clock cycles (200MHz) to move one piece of data, but if the external bus is 100MHz how will that impact the DMA diagram? assume reading memory internal to the part and only the output is in external memory? will it still be 3 cycles to read it, and then the one output cycle will be stretched to match the external bus speed, and the Timing diagram of the memory? ie: the one clock cycle will become 2 for the slower bus speed, and because we have to do a single SDRAM write cycle it will take 3 external bus clocks... so that would be like 6 internal clock cycles, making the full cycle = 3+6 = 9 internal clock cycles long? is that the correct way to look at it?

    We need to determine if we add memory if it will be fast enough for our application so I need to clearly understand the cycles....

    If DMA adds these cycles the question amounts to what is the fastest way to write internal data to external memory using EMIF1? we have to move 24 16bit words very quickly (ADC sampling rate) to record the data to memory... so we can process it later... do you know the FASTEST rate this part will support? ie: what is the fastest WRITE cycle I can generate, ie the fastest sampling rate I can support...

    That is essentially what I need to determine. Is the fastest read from ADC to Write to external memory done with DMA? or is it faster just to use the processor. Assume the processor is doing NOTHING but moving the data, ie: all resources are available for this move...

    essentially, in 200MHz clock cycles what is the minimum clock cycle count to move 24 16 bit words to external memory, we can use SRAM or SDRAM. I'm not sure (certain) from the documentation I can be sure how many clock cycles it takes which is why I'm asking these questions.

    THanks.
  • 0 in reply to Rob Barton
    TI__Guru** 115271 points
    Rob,

    If you are looking for better performance then I would suggest using ASRAM instead of SDRAM. Also copying data from CPU will be faster than DMA. DMA usage is to free-up the CPU MIPS for other critical tasks which DMA can not perform.

    Do you know the data through-put requirement on EMIF interface for your application?

    Regards,

    Vivek Singh
  • 0 in reply to Vivek Singh
    Expert 2220 points

    Yes, we are sampling at 192kHz, using all 24 of your ADC's in 12 bit mode (so read the 16 bit register) so this gives us 1/192000 = 5.2083 useconds to move the 24 samples or just over 1000 200MHz clock cycles to do it.

    Do I just do a assembly routine read the register ie:

    MMOV32 MR0, @_AdcResultRegs.ADCRESULT#
    MMOV32 *MAR1[???], MR0

    Assuming our hardware team can make an external 200MHz bus and we use ASRAM, is this the fastest way to move the memory?

    Can I use your special PWRITE technique on the external bus? I forget offhad how to set it up but I can look it up... would that be faster?

    Essentially if I can know the minimum number of clock cycles it will take then I can specify the requirements to the hardware team on if we NEED the 200MHz external bus or if we can do it with a 100MHz external bus, and how fast the memory needs to be.

    So I need to know the fastest way to write the code, to generate the least number of clock cycles, and I need to know if the EMIF1 inserts any clock cycles, or that type of thing so when I write some code to move it, I know exactly how many clock cycles will be generated so I'm not 'unpleasantly surprised'. Once I know what the part will generate then I can either relax the constraints on the hardware team, or I can tell them that they need to make the full 200MHz bus and we have to get the appropriate speed SRAM to minimize the cycle time.

    Is there any reason the CLA would be faster or the CPU?  Or does it not matter which I use to move the data?
     
    Thanks.

  • 0 in reply to Vivek Singh
    Expert 2220 points

    in the app note it's highly focuses on C/C++.

    In assembler I infer the following:

    1.   I can use direct addressing by loading the DP register, then the offset will be used in conjunction with that to get the 22 bit address?

    2.  I can load the XARn register with the desired value and use indirect addressing.

    So the fastest copy from ADC registers in assembler would be:

    assume XARn is previously set appropriately.

    MOV   AL, @_AdcaResultRegs.ADCRESULT0

    MOV    *XARn++, AL

    and given you stated that rpt and rptb are not supported for this address range we would have to use a compare to a loop counter and a branch as the 'tightest' possible loop, correct?

    MMOV32 MR0, @_AdcaResultRegs.ADCRESULT0

    MOVL