TMS320F28075: CAN Busy bit wait time

Demis Biscaro

Part Number: TMS320F28075

The CAN_IFCxCMD Busy bit is set to one after the nessage number has been written to bits [7:0] in CAN_IFCxCMD. The bit is cleared after read/write action has been finished.

How many clock cycles it takes to finish a read/write action?

Thanks.

over 8 years ago

0 Hareesh Janakiraman over 8 years ago

TI__Guru* 95315 points

Demis,

The next revision of the TRM will have this information:

The IF1/IF2 Command Registers configure and initiate the transfer between the IF1/IF2 Register sets and the Message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command Register. With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in progress. After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM will be completed and the Busy bit is cleared. The maximum number of cycles is needed when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage.

Does this answer your question?

0 Demis Biscaro over 8 years ago in reply to Hareesh Janakiraman

Expert 1145 points

Yes, it does.

Just only a clarification: "4 to 14 clock cycles" refers to CAN peripheral clock or CPU clock?

0 Hareesh Janakiraman over 8 years ago in reply to Demis Biscaro

TI__Guru* 95315 points

CAN peripheral clock.

0 Demis Biscaro over 8 years ago in reply to Hareesh Janakiraman

Expert 1145 points

Ok, thank you Hareesh.

0 Hareesh Janakiraman over 8 years ago in reply to Demis Biscaro

TI__Guru* 95315 points

Demis,
I had some discussion with our Design team and they clarified that these two clocks are the same in this scenario. i.e. the CAN peripheral clock is derived from (and is equal to) the CPU clock.

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TMS320F28075: CAN Busy bit wait time