Concerto question on Bit-Banding

Since your question is about Concerto, I have split it from the TM4C thread: e2e.ti.com/.../314176.
I will let the C2000 folks answer, but if the SRAM is parity or ECC protected, any write, including a single bit write will require a read-modify-write so the proper ECC/parity can be calculated and updated.

Thank you Bob.
I was just searching the forums for info about this subject and jumped on the best fit thread that I saw. Didn't notice it was for another part. The references to code snippets matched the Concerto libraries so I didn't think anything about it. I have more questions on this but will have to wait for tomorrow. End of the day for me :)
Best regards,
Steve

Stephen,

Can you point to the section of document, you are referring here. Bit-band operation is atomic (ARM spec) but this operation is still combination of READ-MODIFY-WRITE in hardware.

Vivek Singh

Vivek, thanks for your response. The manual section I referenced is the TRM spruh22h, section 25.6.4 on Bit-Banding, where it states that in the bit band alias SRAM region: "A write operation is performed as read-modify-write.". Bob Cosby indicated that was because the SRAM internal to Concerto is either ECC or Parity and a read-modify-write operation is necessary to maintain ECC or parity.

The question then is: are the hardware read-modify-write cycles for bit banding in Concerto internal memory atomic or can they be interrupted by an ISR or uDMA or something? Your answer is that even though the bus cycle is read-modify-write, it is still atomic and therefore cannot be interrupted by an ISR.

Thank you and best regards,
Steve Ciricillo