The following thread references the SYNCI/SYNCO delay timing that applies to the F2806x family (and presumably the F2803x family as well):
We are wondering if it is predictable as to whether or not it is 6 or 7 clocks for the purpose of synchronizing 128 devices in series. The difference between 6 or 7 clock cycles adds up quite a bit in the worst case (128 clocks total). My presumption is that the difference between 6 or 7 clocks has everything to do with synchronizing the incoming asynchronous signal with the internal clock. If this is the case, the probability of 6 or 7 clocks should be 50%. Please advise.
Thanks,
Stuart