TMS320F28377S: Maximum ADC Sampling rate.

Hi Mandar,

It is certainly possible to interleave the ADCs to get an increased sample rate, although performance will be a concern. If you need ~8-bits of resolution, this is probably doable.

The ADC conversion time is given in table Table 5-51. "ADC Timings in 12-Bit Mode (SYSCLK Cycles)". From this table, the conversion time when the ADC is operating /4 of the SYSCLK (typical when the CPU is running at 200MHz) would be 44 cycles. The minimum S+H is 75ns @ 200MHz = 15 cycles. Total ADC time between samples therefore needs to be at least 59 cycles. If you want 10MSPS then a sample has to occur every 20 cycles. With 4 ADCs each ADC samples once every 80 cycles, which is > than 59, so possible.

To generate the triggers, you will probably want to use 2 synchronized ePWMs, each with a period of 80 cycles. Each ePWM can generate triggers for two of the ADCs.

As far as memory, 10MSPS * 0.25 seconds = 2.5M samples. Each sample is 12-bit, so they take up a full 16-bit word. There is as much as 106K x 16 on-chip RAM, so you are definitely going to need an external memory connected to the EMIF peripheral. It should be possible for the DMA to move ADC samples to the EMIF, and for the EMIF to write to external memory without CPU intervention.

As far as performance, take a look at the ENOB section in the datasheet table "ADC Characteristics (12-Bit Single-Ended Mode)". In this interleaved cases, the ADCs are not operating in lock-step, so we have to consider the "Asynchronous ADCs" performance specification. For the ZWT package (BGA) this is 10.9 bits and for the PTP pacakge (QFP) this is 9.7 bits. Both should be OK, but note that the single-core F28377x launchpad uses the PZP package, which has bad enough performance in this case that it is "not supported". The PZP package also only has 2 ADCs pinned-out, so you probably would want to get the F283779D dual-core launchpad if you want to use a launchpad as your development platform for this.

In addition to the non-lockstep performance penalty, interleaving ADCs will give you some very significant tones due to ADC-to-ADC gain, offset, and linearity mismatch. We specify the ADC-to-ADC gain and offset error in the datasheet as +/-4 LSBs and +/-2 LSBs (both typical), so I think you should probably be OK to meet 8-bits of performance.

Thank You Devin,

If you are saying reducing resolution to 8 will raise a performance issue then its better to have 12 bit resolution than 8 bit.
one correction is there i have to sample the data for 0.25msec not for .25 sec so i will need 2.5K*16bit to store this data and i think its possible probably without any external memory. (Can i use flash memory to store this data?)
Again as you said one ADC requires 59 SYSCLK cycles for whole process of sampling then its sampling rate will be 59 samples @200Mhz= 3.3898MSPS.
So maybe two ADC 2*3.38=6.779MSPS.

As my requirements are not so strict maybe i will prefer to go with less sampling speed in preliminary study.

Here I do not understand exact meaning of "Asynchronous ADCs".
Does it mean that, I can not employ two ADC's with triggers having time intervals in between cycles of each ADC (to get double sampling rate). as my device does not support it?
Or can i do this thing?
And what is mean by "non-lockstep".

Sorry, If I asked any foolish/basic questions. As i am new to these things its hard to understand everything by just reading the datasheets.
Again, Thanks for your valuable knowledge.

Hi Mandar,

Let's start with the locks-step/asynchronous situation vs. package:

The 4 distinct ADC modules on the chip can potentially interfere with each other under some circumstances.  If you operate them in lock step - the ADCs start and end their conversions at exactly the same time - then there is no interference and you get the maximum ADC performance.  If the ADCs operate fully asynchronously, or with a fixed phase difference (this is the case for interleaving) then there is a performance penalty that varies by package.  On the BGA ZWT package, the ENOB degrades from 11.1 bits to 10.9 bits (not a significant degradation).   On the the QFP 176-pin PTP package the ENOB degrades from 11.1 bits to 9.7 bits...a significant degradation, but it should still meet your requirements.  On the QFP 100-pin PZP package, the ENOB degrades from 11.1 bits to "not supported" (Note: this is the package used by the F28377S launchpad).  You can still configure the ADCs this way, but we don't support the ENOB specification in this configuration (because the performance is bad).  There isn't any issue with reducing the performance to 8-bits...it helps in this case because you can use the ADCs not in lock-step.  Note that you will still get 12-bit results in this case...the performance just won't be as good (but it should still be better than an ideal 8-bit ADC). 

For the sample rate, you will want to go below the maximum sample rate to allow some margin for your triggers and because you likely will want to increase the S+H duration above the minimum (depending on how low impedance your signal conditioning circuitry is, and if you want to get any low-pass filtering from the external R-C on the ADC input).  10MSPS works well because you can run each of the 3 ADCs at 2.5MSPS with plenty of margin above the ~3.4 MSPS max speed.

2.5K x 16 memory locations should be no problem in internal device SRAM.  You can emulate EEPROM with flash, but I don't think it would be nearly fast enough to store the data in real-time (you could store the data in SRAM and then save to flash later if desired).