F28M35H52C: Trip zone interrupt happening twice in a row

I'm using the output of a comparator connected to a GPIO and assigned to Trip5 to trigger an EPWM1TZ interrupt. My problem is that the interrupt always happens twice in a row but I know for certain that the Trip condition is only happening long enough to cause one trip (the qualification time on the comparator is ~800ns and I'm using a pulse generator to make a 900 ns pulse on the comparator input).

When stepping through code in my ISR when I do PieCtrlRegs.PIEACK.all = PIEACK_GROUP2 I see PIEACK go from 0x0002 to 0x0000, then I do the EPwm1Regs.TZCLR.bit.INT = 1 and I notice that the TZCLR INT bit does not clear, the PIEIFR2 register gets set to 0x0001 and the PIEACK gets set back to 0x0002 - it seems like somehow EPwm1Regs.TZCLR.bit.INT = 1 is forcing another interrupt to happen. It doesn't make sense but that's what I'm seeing.

Any ideas? I was wondering if maybe I'm somehow causing two interrupt pulses based on how I set up my epwm1 but the behavior I'm seeing in the registers makes me think it's something else. I initially tried getting the interrupt working without the digital compare but could not get it to work. Is there a better way to set it up?

Here's my isr and init:

__interrupt void epwm1_isr(void)

{

// Acknowledge this interrupt to receive more interrupts from group 2

PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;

EALLOW;

EPwm1Regs.TZCLR.bit.INT = 1; // clear the TZ interrupt

EPwm1Regs.TZCLR.bit.OST = 1; //The one-shot trip condition must be cleared manually by writing to the TZCLR[OST] bit.

EPwm1Regs.TZCLR.bit.DCBEVT1 = 1; // clear the DC evt

EDIS;

}

void InitEpwm1(void)

{

EPwm1Regs.TBPRD = 400;

EPwm1Regs.TBCTR = 0; // Time-Base Counter Register

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up/down

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;

EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // Set Immediate load

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; //Set B high at TBCTR = 0

EPwm1Regs.DCBHTRIPSEL.bit.TRIPINPUT5 = 1;

EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = DC_TRIPIN5; //DC trip select - DCB high input select bits to TZ2

EPwm1Regs.TZDCSEL.bit.DCBEVT1 = TZ_DCBH_HI; //DCB trip event 1 when DCBH high - i.e. when Trip5 high

//EPwm1Regs.TZSEL.bit.OSHT5 = TZ_ENABLE; // enable TZ5 as one shot

EPwm1Regs.TZSEL.bit.DCBEVT1 = TZ_ENABLE; // enable TZ5 as dcbevt1 one shot

EPwm1Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO; //B will go low on event 1

EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWM1B will be forced low on trip event

EPwm1Regs.TZEINT.bit.OST = 1; // Enable Interrupt generation; a one-shot trip event will cause a EPWM1_TZINT PIE interrupt.

//EPwm1Regs.TZEINT.bit.DCBEVT1 = 1;

}