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CCS/TMS320F28075: [Q] piccolo TMS320F28075, CMPSS.CTRIPH -> DCAEVT1.sync

Part Number: TMS320F28075

Tool/software: Code Composer Studio

Dear all,

What I would like to ask is the title.

I want the rising edge of the comparator output to produce sync. signal of ePWM module. 

From now, the output of the comparator is shown properly. 

However, the sync. signal is not working now. ePWM is just running regardless of the rising edge of the comparator output.

Here is my setting as follows. Is there any missed part in my setting?

---------------------------------------------------------------------------------------------------------

EALLOW;

// EPwmXbarRegs
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 1; // CMPSS1.CTRIPH -> MUX0 output -> TRIP4MUXENABLE switch
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1; // TRIP4MUXENABLE enables MUX0
EPwmXbarRegs.TRIPOUTINV.bit.TRIP4 = 0; // Active high

// DCTRIPSEL
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 3; // TRIPIN4 is selected for DCAH

EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2; // generate DCAEVT1 when DCAH=high, DCAL=dont care
EPwm1Regs.TZCTL.bit.DCAEVT1 = 3; // TZ do nothing

EPwm1Regs.DCFCTL.bit.BLANKE = 0; // Blanking window is disabled

EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0; // Use DCAEVT1 directly without filter
EPwm1Regs.DCACTL.bit.EVT1SYNCE = 1; // Enable DCAEVT1.sync
EDIS;

Thank you so muck in advance.

 

  • Hi,

    Can you tell us how you are confirming the CTRIPH signal is occurring? Have you tried to force the sync event within the PWM to verify the sync is correctly setup after the Digital Compare submodule? This would be done with TZFRC[DCAEVT1].

    Is TBCTL[PHSEN] = 1?


    Regards,
    Kris