• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 83 subscribers
  • Views 409 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TMS320F28377D: Is it possible to read and write in General Shared RAM Memory at the same time?

Andreu
Intellectual 510 points
Part Number: TMS320F28377D

Tool/software: Code Composer Studio

Hello everyone,

I am using General Shared RAM Memory to transfer data from CPU1 to CPU2 and my question is whether I must use some kind of handshaking protocol (through IPC) or it is possible to write the data on CPU1 at the same moment it is being read on CPU2.

Many thanks in advance,

Andreu

  • 0
    TI__Guru** 115271 points

    Hi Andreu,

    You don't need handshake for this. CPU2 can read the memory while CPU1 is writing to it. But SW need to make sure CPU2 is not reading the data which CPU1 is updating because in that case CPU2 may get old data (if that's an issue).

    Regards,

    Vivek Singh

  • 0
    Genius 3800 points
    If you write a single 32-bit data in one instruction by CPU1 you can read it by CPU2 but If you write a multiple 32-bit data (for example a structure, or a string) you have to wait the end of writing
  • 0 in reply to Mauro Fantina
    TI__Guru** 115271 points

    Hi,

    If you write a single 32-bit data in one instruction by CPU1 you can read it by CPU2 but If you write a multiple 32-bit data (for example a structure, or a string) you have to wait the end of writing

    I did not understand your comment. Have you seen any issue with writing structure or string? In hardware there is no difference between writing a single 32bit or a structure or string.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Genius 3800 points
    CPU writes 32-bit data in a single cycle by a MOVL instruction,
    CPU write a struct (more than one 32-bit data) in more cycle instructions (more than one MOVL),