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TMS320F28377D: Sharing EMIF (SDRAM) between CPUs

Trevor Heppler
Prodigy 40 points
Part Number: TMS320F28377D

My hardware is using an F28377D connected to an external SDRAM.  The connections and my configuration is working fine.  I can either set it up to be read/written by CPU1 or CPU2.

My question is regarding sharing access to the SDRAM between the two CPUs...  I understand how to use the MSEL_EMIF1 register to grab the EMIF for master access between the CPUs.  This all seems to be working OK.

Please tell me if I am wrong here:

When CPU1 wants to give write access to CPU2, it needs to set MSEL_EMIF1 field to 0 so that CPU2 can grab it.  It also needs to set the peripheral muxing for each pin used by the SDRAM to CPU2.

When CPU2 wants to give write access to CPU1, it needs to set MSEL_EMIF1 field to 0 so that CPU1 can grab it.  Then, CPU1 also needs to set the peripheral muxing for each pin used by the SDRAM to CPU1.

Am I correct about needing to set the peripheral muxing when switching back and forth between CPUs?

What about just for read access?  Is it the same process?

  • 0
    TI__Guru** 115191 points

    Hi Traver,

    Am I correct about needing to set the peripheral muxing when switching back and forth between CPUs?

    No, peripheral muxing is controlled by CPU1 only and once it has been  setup by CPU1 code, only peripheral ownership need to be switch between CPUs and muxing remains same.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 40 points

    OK, just to make sure I understand what you are saying, when configuring the EMIF pins with the GPIO_SetupPinMux function, I could set each of them up like this?

    GPIO_SetupPinMux(38, GPIO_MUX_CPU1, 2); //EM1A0

    Then either CPU can read the memory as it wants without changing any pin setups?

    Why, then, does the following function from the F2837xD_Emif.c file even take CPU number as a parameter?

    void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel)

     -Trevor

  • 0 in reply to Trevor Heppler
    TI__Guru** 115191 points

    Trevor,

    OK, just to make sure I understand what you are saying, when configuring the EMIF pins with the GPIO_SetupPinMux function, I could set each of them up like this?

    GPIO_SetupPinMux(38, GPIO_MUX_CPU1, 2); //EM1A0

    Then either CPU can read the memory as it wants without changing any pin setups?

    This is correct.

    Why, then, does the following function from the F2837xD_Emif.c file even take CPU number as a parameter?

    void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel)

    GPIO_SetupPinmux, which is used in this function, has this argument (to allocate the pins to different CPU when pins are configured as GPIO) hence it was kept in this as well but it was not needed. You can pass "GPIO_MUX_CPU1" for this.

    Regards,

    Vivek Singh