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CCS/LAUNCHXL-F28027F: IBC

Part Number: LAUNCHXL-F28027F

Tool/software: Code Composer Studio

Hi,I m trying to run 3 phase  interleaved buck converter with launchxl-28027f. Could you please provide me the program/files for it.

  • Gannamraju,

    We have not yet implemented any reference designs or kits using the multi-phase buck topology.  In principle, you could look at the buck converter booster pack and supporting code, which implements two independent buck converters:

    http://www.ti.com/tool/boostxl-buckconv

    For a three phase interleaved design you will have to code the PWMs differently (see attached example), and implement current balancing if that is required.

    Regards,

    Richard 

    MPI buck.pdf

  • ;

    Richard Poley said:

    Gannamraju,

    We have not yet implemented any reference designs or kits using the multi-phase buck topology.  In principle, you could look at the buck converter booster pack and supporting code, which implements two independent buck converters:

    http://www.ti.com/tool/boostxl-buckconv

    For a three phase interleaved design you will have to code the PWMs differently (see attached example), and implement current balancing if that is required.

    Regards,

    Richard 

    (Please visit the site to view this file)

    Hi i am trying to generate 3 phase interleaved buck converter.I want 120 degree phase shift.i am not generating for synchronous buck converter.

    i want pwm1:epwm2A

    PWM2:epwm2B

    Pwm3:epwm3A.

    My program is shown  below.Could you check whether the logic is correct?

    COULD YOU PLEASE HELP ME

    THANKYOU

    EPwm1Regs.TBPRD = 600; // Period = 601 TBCLK counts
    EPwm1Regs.CMPA.half.CMPA = 200; // Compare A = 350 TBCLK counts
    EPwm1Regs.CMPB = 200; // Compare B = 200 TBCLK counts
    EPwm1Regs.TBPHS = 0; // Set Phase register to zero
    EPwm1Regs.TBCTR = 0; // clear TB counter
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
    EPwm1Regs.AQCTLA.bit.PRD = AQ_SET;
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
    EPwm1Regs.AQCTLB.bit.PRD = AQ_CLEAR;

    EPwm2Regs.TBPRD = 600; // Period = 601 TBCLK counts
    EPwm2Regs.CMPA.half.CMPA = 200; // Compare A = 350 TBCLK counts
    EPwm2Regs.TBPHS = 400; // Set Phase register to zero
    EPwm2Regs.TBCTR = 0; // clear TB counter
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero
    EPwm2Regs.AQCTLA.bit.ZRO= AQ_SET;
    EPwm2Regs.AQCTLA.bit.CAU= AQ_CLEAR

  • i mean pwm1=epwm1A;
    pwm2=epwm1B;
    PWM3=ePWM2A;
  • Gannamraju,

    You will need to implement something similar to the waveforms I sent you, even if you are not driving synchronous buck converters.  You cannot do this with two PWM modules, because each module has only two comparators against which edges can be placed.  You will require three separate PWM modules, with time-bases synchronised as shown in the diagram.

    To illustrate the limitation, your code switches both PWM1A and PWM1B on the period event, so it cannot be correct in a 3-phase application.

    Regards,

    Richard