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TMS320F28075: eQEP - Position Counter Reset on the First Index Event not available after SW reset

Aurélien
Prodigy 120 points
Part Number: TMS320F28075

Hi,

I'm using the eQEP peripheral on the TMS320F28075. I configure it to manage the position counter reset on the first event (QECTL[PCRM] = 10). Just after a hardware reset, the FIMF is correctly detected and the counter is loaded with the value of the QPOSINIT or QPOSMAX as expected. Then, I use the SW reset (QEPCTL[QPEN] = 0), the QEPSTS[FIMF] flag is reset. But when the peripheral is released from the SW reset state (QEPCTL[QPEN] = 1), the next first index condition is not detected and the counter is not loaded as expected.

Is there a solution to manage a new first index detection by software without resetting the microcontroller?

Thanks in anticipation.

  • 0
    Guru 30330 points
    Hello,

    You should be able to reset the counter without resetting the device. I will be looking into this tomorrow and will reply by the end of the day.
  • 0 in reply to Mark Labbato
    Guru 30330 points

    Hello,

    I have confirmed this behavior on the bench but would like to make sure that we are operating under the same conditions. Can you please share your full eQEP configuration code to verify?

  • 0 in reply to Mark Labbato
    Guru 30330 points
    On further debug, You can set and clear the device level software reset for the module (DevCfgRegs.SOFTPRES4.bit.EQEP1). You do need completely re-initialize the module, but the FIMF is able to be set again.

    I have submitted a question to our design team for further information on this behavior. If you can send your EQEP configuration, it would definitely help.
  • 0 in reply to Mark Labbato
    Prodigy 120 points

    Hello Mark,

    Thank you for your investigations.

    Here is my configuration:

    /* Unlock register protection write on protected registers */
EALLOW;

/* Enable peripheral clock */
CpuSysRegs.PCLKCR4.bit.EQEP2 = 1u;

/* Release register protection unlock */
EDIS;

/** Reset counter on first index */
EQep2Regs.QEPCTL.bit.PCRM = 2u;

/* Rising edge latches position counter on rising edge of the index signal */
EQep2Regs.QEPCTL.bit.IEL = 1u;

/* Set the max counter value to the max 32 bits value */
EQep2Regs.QPOSMAX = 0xFFFFFFFFu;

/** Set the initialisation value of the counter to the specified input value */
EQep2Regs.QPOSINIT = IIndexCalibValue;

/* Enable position counter */
EQep2Regs.QEPCTL.bit.QPEN = 1u;

    Best regards

  • 0 in reply to Aurélien
    Guru 30330 points
    HI there,

    I have submitted the question to our design team for their input. There is no eQEP in-module reset that will reset the state machines and other status such as the FIMF flag. It is odd that the FIMF bit is cleared when the QPEN is cleared but cannot be set again after the position counter is re-enabled.

    On F2807x, F2837xS, F2837xD, and F28004x devices, the SOFTPRESx bit will allow the eQEP to be fully reset without affecting other functions of your system, but the eQEP will need to be reinitialized after. On older devices, the only path to reset the FIMF functionality will be to reset the device, as you have seen.

    I will let you know when I have a response from our design team.