TMS320F28335 - Manual CAN Bus Recovery after Bus Off

Carlo,

The CCR bit is a reliable indicator of the node having entered the bus-off state. If that is bit is set, the node is in bus-off. Once this state is reached, CANREC indeed changes its function (to counting 11-bit recessive times to 128). You are correct that once this has been monitored, it is safe to clear CCR and come out of bus-off. Are you sure BO bit is indeed set to 1 upon bus-off but gets cleared automatically without the code writing to CANES register?

Hi Hareesh,

Thank you for your reply. 

To the best of my knowledge I have disabled every write access in the application software to the CANES register. When the Bus Off occurs I do see the EP & EW flags beeing set and those flags are also not reset. With the BO flag this is however different.

With regard to the CCR Bit:

I have checked that once the bus off occurs the CCR Bit of the matching bus is set continuously. However, when the bus off condition is removed the CANREC counter does not change its value although the CCR Bit is still set permanently. Other nodes on the same bus also resume their normal operation. Therefore I assume that the bus is in fact ok.

On doing a manual reset of the CCR Bit for my bus, despite the current state of CANREC for my bus (is still 0), my node also recovers and operates normally. Unfortunately with this setup I cannot match the required timing for the bus recovery, since I am missing the reference point for when the bus actually changed to operational state.

Best case for me would still be to use the original ABO bit for the bus recovery. Is there any indication from the CAN Controller when it has performed a bus on due to the Bit ABO? In this case I could adapt the recovery of the CAN sending of the application based on such indication to match the required timing.

Best regards.

Carlo,

            How many nodes are there on your network? When the F28335 goes bus-off, what do the other nodes on the network do?

You say "when the bus off condition is removed the CANREC counter does not change its value although the CCR Bit is still set permanently." When the bus-off condition is removed, CCR should get cleared automatically (if ABO=1). I also don’t understand what you mean by "CANREC counter does not change its value ". Please read the excerpt from the module spec below:

After reaching the „bus off“ state the transmit error counter is undefined while the receive error counter changes its function. After reaching the state „bus off“, the receive error counter is cleared. It will then be incremented after every 11 consecutive recessive bits on the bus. These 11 bits correspond to the gap between two telegrams on the bus. If the counter reaches the count 128, the module changes automatically back to the status „bus on“ if this feature is enabled (Auto Bus On bit (ABO) in Master Control Register (MCR) set.). All internal flags are reset and the error counters are cleared.

Per the last statement, BO bit is cleared and CANREC is made 0 upon exiting the bus-off condition.

Regarding your last question " Is there any indication from the CAN Controller when it has performed a bus on due to the Bit ABO? ", you should see the CCR bit cleared upon exiting bus-off. You could poll the CCR bit to determine the moment when the node exits bus-off.

Hi Hareesh,

I hope you had a nice weekend.

The current configuration of the ABO bit is ABO = 0 and therefore "manual" bus on. 

What I referred to by "when the bus off condition is removed the CANREC counter does not change its value although the CCR Bit is still set permanently." is, that the even though the CCR bit is still active (after a bus off occurred),  the ABO bit is set to 0 and the bus off condition removed the CANREC counter is not incrementing. It always stays at CANREC = 0 (no manual bus on was done).

As I understand your first reply "If that is bit is set, the node is in bus-off. Once this state is reached, CANREC indeed changes its function (to counting 11-bit recessive times to 128)." I am expecting to see an incrementing CANREC counter. For the above described configuration.

With regard to my second question "Is there any indication from the CAN Controller when it has performed a bus on due to the Bit ABO?" As far as I have tested it the CCR bit is not active during bus off when the ABO bit is set to 1. In  "sprueu1" the description for the CCR states: "The CCR bit will also be set upon a bus-off condition, if the ABO bit is not set." So I wasn't expected to see any change in the CCR bit when ABO = 1 during bus off/bus on recovery.

That’s why I was asking, if there is any indication for a state change of the controller due to the ABO = 1 configuration.

To answer your questions: “How many nodes are there on your network? When the F28335 goes bus-off, what do the other nodes on the network do?”

For my testing (this is only a bench test setup) the CAN consists of three different nodes: my test system, a vector CAN case for monitoring the messages and a third CAN node based on the SJA1000. 

What I referred to by "when the bus off condition is removed the CANREC counter does not change its value although the CCR Bit is still set permanently." is, that the even though the CCR bit is still active (after a bus off occurred), the ABO bit is set to 0 and the bus off condition removed the CANREC counter is not incrementing. It always stays at CANREC = 0 (no manual bus on was done).

Answer--> Once the bus-off condition is removed, why would CANREC increment? Are you expecting to see it at 128? I am suspecting it is cleared to 0 after counting up to 128, but the node itself does not participate in any communication until CCR is cleared to 0.

As I understand your first reply "If that is bit is set, the node is in bus-off. Once this state is reached, CANREC indeed changes its function (to counting 11-bit recessive times to 128)." I am expecting to see an incrementing CANREC counter. For the above described configuration.

Answer--> Please clarify "incrementing". The incrementing and subsequent clearing happens at a speed that is not observable by the human eye. Did you try taking a snapshot of the register and filling a memory buffer?

Perhaps we have reached a stage where a conference call may be better. I have a feeling I have not understood your concern well.

Carlo,

I wrote a test-case to verify this and I am able to see the CANREC counter increment correctly. I filled the CANREC values in a buffer. After CANREC counts 128 occurrences, it is reset to "0". CCR bit still stays as 1. Node comes out of bus-off when it is cleared.