This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28377S: Buffered DAC clock

Part Number: TMS320F28377S
Other Parts Discussed in Thread: CONTROLSUITE

Hello Team,

I have a customer who is trying to find out the max clock for the buffered DAC for the F28377S device. After going through the clock structure and the DAC block diagram the customer has come with the following feedback :

" I painstakingly  studied the clocking system. Here is the scheme related to buffered DAC. In this  scheme XL(reference osc)-> PLL (multiplier)-> PCLKCR13(gate for DACa). According to it the DAC clock is set to SYSCLK of 200 MHz. Am I correct? I do not mess with system PLL which sets up CPU clock that is done by SysCtrl.c file. I am asking a simple question What is the buffered DAC clock, that I as well draw in the attached picture. "

How is the buffered DAC gated. 


Thank you for your time,

 

Kishen