In section 25.3.5.5 procedure B
item 4. states we should program the SDRAM_CR to match the characteristics of the attached SDRAM.
Q: If we use the bit based mode of setting each parameter in SDRAM_CR, will this trigger multiple auto-initialization sequences? Since section 25.3.5.4 says that if we write to any of the lease significant bytes... this says if we write to the NM, CL, IBANK, PAGESIZE individual will that trigger 4 auto refreshes?
To only get one auto refresh does this force us to do it the .all way?
// Set bus width to 32 bits
Emif1Regs.SDRAM_CR.bit.NM = 0;
// Set the CAS latency for read cycles
Emif1Regs.SDRAM_CR.bit.CL = 2;
// Set the parameters of the chosen memory
Emif1Regs.SDRAM_CR.bit.IBANK = ?;
Emif1Regs.SDRAM_CR.bit.PAGESIGE = ?;
