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CCS/F28M36P63C2: ADC1/2 always enabled on device start and cannot be changed

Part Number: F28M36P63C2
Other Parts Discussed in Thread: CONTROLSUITE

Tool/software: Code Composer Studio

When powering-up the F28M36, I find that the ADC control registers on the C28 core (ADCn:ADCCTL1) have a value of 0x4000. This can be seen at any time:

  • The initial entry point (first assembly instruction, before any initialisation)
  • At the start of the main() function
  • Before and after calls to the MWare functions InitSysCtrl() and InitPeripheralClocks().

Starting the M3 core or not doesn't affect it.

Referring to "Table 10-6. ADC Control Register 1 (ADCCTL1) Field Descriptions" in the Technical Reference Manual (SPRUHE8D), this means that the ADCENABLE bit is set, though the preceding Figure 10-17 says this is read/write and initialises to 0 (R/W-0)

It is impossible to write a 0 to this bit - doing so does nothing, though you can set other bits, for example 0x00E0 and 0x0002. Resetting with a write of 0x8000 also does nothing to the enable bit.

There doesn't appear to be anything relating to the ADC registers in the GEL files used (functionally the same as in controlSUITE). There doesn't seem to be a mention of this bit in the errata (SPRZ375I).

Is it expected that this bit cannot be changed and the ADCs are always enabled? Is it safe to assume that, or should a write be made to the bit anyway?