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TMS320F28075: Is there a condition for the ADC reference of VREFHIA, VREFHIB, VREFHID at power-on?

ck2_m
Intellectual 720 points
Part Number: TMS320F28075
Other Parts Discussed in Thread: OPA320, OPA350

Hi, Everyone

I need your help.

I have a question about the power up sequence of the TMS320F28075.
Is there a condition for the ADC reference of VREFHIA, VREFHIB, VREFHID at power-on?

About the power-up sequence The data sheet contains the following conditions.

5.7.1.2 Power Sequencing
・An external power supply must be used to supply 3.3 V to VDDIO, VDD3VFL,VDDOSC, and VDDA. VDDIO, VDD3VFL, VDDOSC, and VDDA should be powered up together and be kept within 0.3 V of each other during operation.
・Before powering the device, no voltage larger than 0.3 V above VDDIO should be applied to any digital pin, and no voltage larger than 0.3 V above VDDA should be applied to any analog pin.
・When using an external supply to supply VDD, the voltage on VDDIO should be greater than VDD or no less than 0.3 V below VDD at all times.
・The supplies should ramp to full rail within 10 ms. When using the internal VREG, the power sequence is handled internally.

Best regards
Maekawa

  • 0
    TI__Guru 60865 points
    Hi Maekawa,

    VREFHI must be less than VDDA at all times.

    Since VREFHI < VDDA during functional operation, the easiest way to handle this is to power the op-amp that is driving VREFHI (we suggest OPA320 or OPA350) with VDDA. This will ensure that VREFHI never exceeds VDDA both during normal operation and during power-up.

    If you use a different op-amp, you may need to take other precautions to ensure that VREFHI doesn't exceed VDDA during power-up.
  • 0 in reply to Devin Cottier
    Intellectual 720 points

    Hi Devin,

    Thank you for Reply.

    Best regards,