LAUNCHXL-F28377S: SPI communication with DMA have fluctuate values

Hi Stefan,

I'm going to be looking into your issue. Do you have any additional details to share since posting?

Just to confirm, the issue is that the slave device is receiving data out of order? Could you provide some screenshots of the specific issue to make sure we understand?

Regards,
Kris

Hi Kris,

thank you for your support.

That you have more information, here is my test application:

1. I started the programm from Master (Laptop) and Slave (PC) in Debug-Modus and I didn´t change my values.
 The values in rdata_array from Master and Slave are correct and static, and stable.

2. I take my oszilliscop and linked one channel to STE Pin (Enable Pin) for trigger. The other channel is first linked to MOSI (picture), then to MISO (picture) and then to CLK (picture). After I linked my oszi to CLK, the values in rdata_array began to change to false values. The signals are stable and looks good in oszi, but the value in rdata_array changed. If I linked my oszi again in MOSI, the values were correct again and static / stable.

3. Now I changed at my Master (Laptop) the value in Debug-Modus from 0 to 20. The values are jumping around and were not correct! They jumping at rdata_array from Master AND from Slave! So with this status I made a picture with my oszi in MOSI, MISO and CLK. After I linked it to CLK the values switch to the static / stable AND correct value!! Signals in oszi are stable and look well.

4. Changed values at Slave -> nothing is happened (changed more than two times!)

5. Changed values at Master -> nothing is happend (changed more than two times!)

6. Connect oszi to CLK again -> rdata_array values jumping and weren´t correct!

7. Now I connect my oszi to MOSI -> rdata_array sill wasn´t correct

8. Now connect to MISO -> Values in CodeComposerStudio are static and correct, but in the wrong case in rdata_array! What should be in rdata_array[0] is in [1] and [1] is in [0]... From Master AND Slave!

After this test im confused again. It seems that my test application isn´t ok for this test. But already the signals at my oszi are static and ok. So i don´t know why the µC im Debug-Modus in CodeComposerStudio doesn´t show the correct values! Most mysterious is the mirrored result in rdata_array. I mean, the signal is the same like befor... I can´t explain it.

I hope you can tell me something about my wrong testing. -> ZIP file: pictures.zip

Many thanks in advance!

Best wishes

Stefan

Stefan,

Again to ensure I am understanding the issue-

The program works fine when the probes are not connected. As soon as you connect the probes to the data lines, then the data is being read incorrectly. Is that an accurate description of the issue?

- What frequency is the SPI communication at?
- Have you looked at the clock polarity and phase settings to ensure they are configured correctly?
- Do you have any through-hole resistors that you could try putting inline?

Regards,
Kris

Hi Kris,
it´s not correctly. The programm is insane without the probes from oszilliscope too. I tested it again right now. I startet the programm from master and slave without oszilliskop. At first the rdata_array was mirrored ([0] was in [1] and [1] in [0]). If I set from Master the sdata_array[0] value from 0 to 20, the rdata_array is mirrored in CodeComposerStudio too. So the problem is still there! But with oszilliscope probes i can influence the result in codecomposerstudio. If i connect one probe it can be make stable the values in CodeComposerStudio and/or it makes the values in the correct order in rdata_array. For summary: Althought the signals are stable at oszilliscope, the programm in CodeComposerStudio Debug-Modus show sometimes the correct results in rdata_array, and sometimes, at some determined values, the false or the mirrored values.

To your questions:
- What frequency is the SPI communication?
The SPI Clock is at 2 MHz (sysclock = 200 MHz; LSPCLKDIV = /1; --> LSPCLK = 200 MHz; SPI_BIT_RATE = 0x63 --> SPICLKA = 2MHz)
The transmission speed is at 2kHz (it transmit every 0.5ms). The Timer0 is starting CH6 and CH5 from DMA.

-Have you looked at Clock polarity and phase settings? Are they correctly?
Master and Slave have the same settings:
CLKPOLARITY = 0 and CLK_PHASE = 0

- Do you have any through-hole resistors that you could try putting inline?
At my testings I connected the master with slave without resistors. After your post I tried to put 470R Resistors inline. If I put one to SPICLK, it smooth my signal to much an the results in CodeComposerStudio aren´t stable and correct. If I only have the Resistors in MISO and MOSI, the same problem as befor is there. It changed / mirrored the values in rdata_array. (From Master and Slave!)


Summary:
# Programm isn´t working at some values from Master sdata_array. At other values the programm works... (it´s *Insane*)
# Either the rdata_array from Master and Slave are mirrored, or the rdata_array results aren´t correct.
# If I link my oszilliscope with my test wiring, I can sometimes influence the problem or I generate one of the problems.

So that´s why I ask: "Is my programm with DMA the problem? Or is it my test wiring completely false ? Or is the frequency for SPI to high?"
Maybe you have some ideas.

Regards,
Stefan

Stefan,

The first thing we need to do is to try to get your setup cleaned up a bit. There is a lot of external wire which introduces a lot of extra load and noise onto the pins.

It looks like you are using female to male jumper wires which is why the breadboard is required. Do you have any female to female jumper wires that you could use to go directly from one launchpad to the other? This would cut the wire lengths in half and may resolve the issue. If you do not have any female to female jumper wires, you could also use the alligator clamps in the picture to just clamp the jumper wire directly onto the pin on the other board.

Regards,
Kris

Hi Kris,
I have female to female jumper wires. I connected the Lauchnpad together and did the test again:
1. After start of the programm, the right values in the right order are in rdata_array from Master and Slave. (all is correct)
2. I changed the sdata_array value in Debug-Modus from Master -> sdata_array[0] from 0 to 20. Now the values in rdata_array from Master and Slave aren´t correct and jump around. (they aren´t static)
3. I changed the sdata_array value in Debug-Modus from Master -> sdata_array[0] back to 0 and sdata_arry[1] from 1 to 20000. Now the values are sometimes mirrored in rdata_array from Master and Slave. The switch its case in rdata_array.
4. I changed the sdata_array value in Debug-Modus from Master -> sdata_array[1] back to 1. Now the start conditions are set again. The values are correct in rdata_array from Master and Slave. There aren´t jump around and aren´t mirrored.

Do you think it´s still a problem with my test wiring?

Best wishes,
Stefan

Hi Stefan,

I'm going to try and get your code running to debug the problem. This may be slightly delayed while I replicate the hardware setup and get the code running.

Regards,
Kris