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TMS320LF2407A: Interrupt driven ADC results to DMA adressing issue

Part Number: TMS320LF2407A

We are writing a code for interrupts wit ADC. The ADC's Outputs from the result zero cannot be moved to ant DMA location( we are moving to predefined variables in DP100h).

  Here is the code we have a problem with.

GISR2:                     <--------------------------------------------ISR Starts Here.            Go Down To View the problematic part 
                        LDP #0h
                        SETC INTM ;disable all interrupts

                         SETC SXM 
                         SETC OVM
                         CLRC SXM
                         CLRC OVM
                         CLRC CNF ;clear cnf bit
                         LDP #0e8h ;load dp to event manager page
                         SPLK #0FFFh,EVAIFRA ;clear eventmanager interrupts
                         SETC XF ;set XF flag


                         LDP #0E1h ;set data page to adc
                         SPLK #04000h,ADCTRL2 ;RESET ADC

                         SPLK #02000h,ADCTRL2 ; Start the conversions

CHK_EOS1: 

                        LACC ADCTRL2 ; Wait for SEQ1 Busy bit to clear
                        AND #0001000000000000b ; BIT12 is loaded into TC bit of ST1
                        BCND CHK_EOS1,NEQ ; If TC=1, keep looping.


                        LACC RESULT0 ; Load conversion result of Channel 1
                                                          ;  from Ch1 buffer register into ACC
                        CLRC SXM
                        NOP ; enabling logic shifts of the accumulator.
                        RPT #5 ; Repeat the following instruction 6 times
                        SFR
                        NOP 
                        AND #3FFh
                        NOP ; Shift right (6 times since ADC is 10-bit)
                       

                       LDP #100h

                      SACL ADC_OUT   <<<<<<<-------------------------------------------------------- A Predefined variable. Which is not updating according to Result0 even when ADC input   

                                                          <<<<<<<-----------------(cont)  is updating Result0 in the ISR.   

                       CLRC INTM ;enable the interrupts 

                                                     CLRC XF
RET

  • Kartikeya,

    Can you confirm that the RESULT0 register is updating as expected, but it's simply the accumulator store that is not working?

    Are you trying to store the accumulator using direct addressing? If so, I think that you need a "#" in front of your ADC_OUT variable in order to do so.

    Also, the peripheral user guide recommends inserting 4 NOPs before polling the SEQn BSY bit; or the INT FLAG SEQn bit can be polled without NOPs.

    -Tommy