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TMS320F28035: Questions about warm reset

Young Hu
Expert 4185 points

Part Number: TMS320F28035

Hi Champs,

My customer has several questions about F28035 warm reset as follows. They want to get the minimum delay time, because they want to their DCDC output would be smooth even if MCU was reset by accident. Would you kindly help to answer them?

1. What's the delay time from pulling XRS high to getting into main()? One GPIO toggling was used to indicate the delay time by my customer, the delay time is about 7~8ms, which is too long from my customer's point of view;

2. After warm reset, are the functions and variables copied to RAM still reliable? If the answer is yes, they will skip the mem_copy functions after warm reset by accident.

3. During warm reset, would VREG be reset also?

4. Is there any method to know the last reset source after reset? 

Thanks a lot.

BR,

Young

  • 0
    Guru 30330 points
    Young,

    Can you share a little more information on how the customer is boot time? is the GPIO toggle placed as the first line in main after configuring the GPIO to output mode?

    VREG would not be reset. This is a layout time decision. If the VREGENZ is tied low, the device will operate using the internal voltage regulator.

    I am doing a bit more research on your other questions and should get back to you tomorrow.
  • 0 in reply to Mark Labbato
    Guru 30330 points
    Young,

    First, a rough estimate of the boot time is 100us. This is calculated with the th(boot-mode) on Table 5-3 REset (/XRS) Timing Requirements. If the reset is forced externally or driven by the Watchdog, SYSCLK will be 10MHz. The boot pins are required to be held for at least 1000 cycles of SYSCLK. 7-8 ms seems like a very long time to boot your application. Please answer my previous question regarding how you are measuring this time. However, If you are not toggling the GPIO until after you configure the PLL and you are using the on-chip XTAL, 7-8 ms may be reasonable due to the startup time seen in Table 5-4 Reset (/XRS) Switching Characteristics.

    The RAM on 2803x devices are not initialized to zero, so other than the boot ROM reserved RAM, it should still be valid and usable. This does NOT hold true if there is a POR reset. in this case, the RAM contents cannot be guaranteed.

    There are not many resets on F2803x. You can detect if a reset was caused by a missing clock in the MCLKSTS register and also a watchdog reset in the WDCR register.

    Please let me know if you have additional questions or need more clarification anywhere.
  • 0 in reply to Mark Labbato
    TI__Expert 4185 points
    Hi Mark,
    You are right, it is the GPIO toggle as the first line in main
  • 0 in reply to Young Hu
    Guru 30330 points
    Young,

    Can you share some oscilloscope plots of the full boot time? Please provide a capture of the POR to GPIO toggle, including XRSn, the GPIO toggle, and the Power Supplies. Next, provide a similar scope capture of a warm reset.
    What boot mode are you using? - Boot to Flash, SCI Boot, etc,
    Do you see the same behavior on multiple devices? if not, how much variation is there in the boot time.
    Does the boot time vary with every reset, or is it consistent.

    Realistically, there is no way to shorten to boot time of the device. The boot ROM is programmed at TI during production into OTP.

    If you can answer the questions I have asked, we might be able to explain the behavior at the very least.
  • 0 in reply to Mark Labbato
    TI__Expert 4185 points
    Hi Mark,
    Customer found there were so many global variables to be initialized during startup. And this question can be closed.
    Many thanks.
    BR,
    Young
  • 0 in reply to Young Hu
    Guru 30330 points
    Young,

    Thank you for the update. I will close out the thread

    Regards,
    Mark