Hello,
It is described in 【1.1.7.2 Transmitter Signals in Communication Modes】 on page 18 of sprugh1c as follows.
Notes:
1. Bit TXENA (SCICTL1, bit 1) goes high, enabling the transmitter to send data.
2. SCITXBUF is written to; thus, (1) the transmitter is no longer empty, and (2) TXRDY goes low.
3. The SCI transfers data to the shift register (TXSHF). The transmitter is ready for a second character
(TXRDY goes high), and it requests an interrupt (to enable an interrupt, bit TX INT ENA ? SCICTL2,
bit 0 ? must be set).
As a result of verification,
I think that 1 bit delay will occur according to the baud rate cycle before transmission starts.
Please let me know the delay time from writing data to SCITXBUF and outputting data from SCITXD via TXSHF register.
Best Regards,
Koichi
