Hello,
I have noticed something strange when trying to use HRPWM on the F28379D. The set up code I am using is shown below. I then launch into an infinite loop that slowly increases the CMPA:CMPAHR register.
The odd behaviour is:
If HRCNFG.AUTOCONV bit is set AND HRCNFG.HRLOAD = HR_CTR_PRD (01) then changes to the CMPAHR have no effect.
If HRCNFG.AUTOCONV bit is set AND HRCNFG.HRLOAD = HR_CTR_ZERO (00) then all is OK: I can poke CMPAHR with values from 0x0000 through 0xFF00 and this increases the on time of the pulse through one TBCLK cycle.
Further, If HRCNFG.AUTOCONV bit is not set, then all is OK regardless of HRCNFG.HRLOAD. Obviously, in this case there is no scaling so I poke CMPAHR with values from 0x0000 through (HRMSTEP<<8) to achieve the same effect of the pulse increasing over one TBCLK cycle. HRMSTEP was set by calling the SFO function during initialisation and is 59 on my processor.
Note that in my set up I am using the global load feature so, if I understand it correctly, the HRCNFG.HRLOAD shouldn’t have any effect. I have set shadow load of CMPA:CMPAHR to occur on TBCNT = TBPRD (GLDCTL = 0x83 and GLDCFG = 0x707). However, if I change this to TBCNT = zero (GLDCTL = 0x81) I observe exactly the same behaviour as stated above.
Also:
The HRCNFG register does not appear to be protected by EALLOW as stated in the reference manual: I can poke it from the watch window in CCS.
Note that this is not actually a problem for me: I just set HRCNFG.HRLOAD to 0 and it all appears to work fine: just interested in what is going on here and why this behaviour is not mentioned in the manual.
Cheers,
John Wilkes.
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My set up code follows, all other registers are left at default:
EALLOW;
/* Global load enabled: load on every counter = period event */
EPwm1Regs.GLDCTL.all = 0x83;
/* Use global reload for: AQCSFRC, AQCTLB, AQCTLA, CMPB, CMPA & TBPRD */
EPwm1Regs.GLDCFG.all = 0x707;
EDIS;
/* TBCTL : all default except /1 clock divide (/2 is done prior to ePWM */
/* module) and set up count mode */
EPwm1Regs.TBCTL.all = 0xC030;
/* Output A only - B is set as inverse of A as part of HR setup */
/* Output goes high on ZERO and low on CMPA; */
EPwm1Regs.AQCTLA.all = 0x12;
/* Period 500kHz = 199 */
EPwm1Regs.TBPRD = 199;
/* Only using CMPA - set in application, but set 50% default */
EPwm1Regs.CMPA.bit.CMPA = 99;
EPwm1Regs.CMPA.bit.CMPAHR = (1 << 8); // Initialise HRPWM extension
/* High resolution set up*/
EALLOW;
EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge of CMPA
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // Compare register controls MEP
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_PRD; // This is the issue!!!
EPwm1Regs.HRCNFG.bit.SELOUTB = HR_INVERT_B; // Make B output from inverted A output
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion logic
EDIS;
