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TMS320F28335: F28335 ADC and DMA configuration

stephane stephane
Prodigy 80 points

Part Number: TMS320F28335

Hello,

I ve tried to use the example provide for the ADC confiugration and DMA which include the following configuration:


// Configure DMA Channel
DMADest = &DMABuf1[0]; //Point DMA destination to the beginning of the array
DMASource = &AdcMirror.ADCRESULT0; //Point DMA source to ADC result register base
DMACH1AddrConfig(DMADest,DMASource);
DMACH1BurstConfig(3,1,10);
DMACH1TransferConfig(9,1,0);
DMACH1WrapConfig(1,0,0,1);
DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,SYNC_DISABLE,SYNC_SRC,
OVRFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);

It is supposed to acquire 4 channels with 10 samples per channel.

When trying to change this configuration, for instance 2 channels with 1024 samples by channel, it fails.

I do update as follow:

MACH1BurstConfig(2-1,1,1024);
DMACH1TransferConfig(1024-1,1,0);
DMACH1WrapConfig(1,0,0,1);

IS this configuration is correct for 2 channels?

Thank you

  • 0
    Guru 30330 points
    Hello,

    Can you be a little more descriptive about how it is failing? Is the program crashing? Is your buffer size large enough to handle all of the data?
    The configuration is correct. I have just verified it on my bench setup. The DMA is configured to do 1024 bursts of 2 words, and will jump 1024 words between each word in the burst.
  • 0 in reply to Mark Labbato
    Prodigy 80 points

    Hello,

    Thank you for your anwer.

    The issue is that when i check the buffer supposed to acquired 2 distinct ADC inputs (B0 and B1), the content is not valid .

    My goal is to acquire those 2 ADC inputs and collect them in a buffer where all the samples of the 1st channel are stored in the upper part, and the samples

    of the second channel in the lower part of the buffer.

    For instance in the buffer from range to 0 up to 1023, the sample number 1 ... up to sample number 1023 of the ADCIN B0,

    and in buffer from range to 1024 up to 2047 , the sample number 1 ... up to sample number 1023 of the ADCIN B1,

    Is it clearer?

    Regards

    Stephane

  • 0 in reply to stephane stephane
    Prodigy 80 points
    I provide here the ADC confiugration i use :
    AdcRegs.ADCTRL3.all = 0x00E0u;
    DELAY_US(100);
    AdcRegs.ADCTRL1.bit.SUSMOD = 3u;
    AdcRegs.ADCTRL1.bit.CPS =0u;
    AdcRegs.ADCTRL1.bit.ACQ_PS = 0;
    AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x1;

    AdcRegs.ADCTRL1.bit.SEQ_OVRD =1;


    AdcRegs.ADCTRL1.bit.CONT_RUN = 1u;
    AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;

    AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // 0 Non-Cascaded Mode

    AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
    AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
    AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x8;
    AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x8;
    AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 1; // Set up ADC to perform 2 conversions for every SOC