Hi all,
I am looking to use the TMS320F28377S to implement an average current mode control law inner loop and modulator for an interleaved buck converter. The plan is to use an external FPGA to handle the outer loops. The design requires multiple 16-bit signals to be passed at a 1MSPS rate. The uPP peripheral would seem to be up to the task, but the 64 byte read quantization in the uPP DMA makes this impossible. At best it is possible to shift 781250 data frames per second. This effectively limits the data rate; is there anyway to get around the 64 byte limitation of the DMA, or should I look at a different data interface such as the McBSP?
Best regards,
Lance Hummel