TMS320F28375D: PWM max freq

I'm having difficulty doing a simple task.

The part is 200MHz, so I have set the /2 as you have indicated above.

Now if I set both prescalers to 0, is the TBCLK = 100MHz?

I'm trying to set the period to 240kHz using the 100MHz clock input, but when I measure the output on the scope I get weird (not 240kHz) results.

I can manipulate the TBPRD register, but as a test case use figure 14-24...

So if I set TBPRD = 4 and set A to be 50% ie CMPA = 2 and B to be 75 % CMPB = 1 with the prescalers set to HSPCLKDIV = 0, CLKDIV = 0
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
I do not get the expected output frequency.

The main question is how do I set the prescalers and the period in up down count mode (CTRMODE) to get a 240kHz counter period (regardless of how I set the A & B) I can use the scope and adjust the TBPRD to get 240Khz, but it's not behaving as described in the manual.

Am I exceeding limits? must I prescale it to a lower value? Am I not configuring something?

Using the equation in figure 14-6 Tpwm = 2*TBPRD * Ttbclk I computed
Tpwm = 1/240e3 and Ttbclk = 1/100e6 (the /2 200MHz) to get the period must be 208... is this correct?

Rob,

Rob Barton said:

The part is 200MHz, so I have set the /2 as you have indicated above.
Now if I set both prescalers to 0, is the TBCLK = 100MHz?

Correct.

Rob Barton said:

Using the equation in figure 14-6 Tpwm = 2*TBPRD * Ttbclk I computed
Tpwm = 1/240e3 and Ttbclk = 1/100e6 (the /2 200MHz) to get the period must be 208... is this correct?

Correct.

Have you tried the example in C2000Ware?

Regards,

David

Thanks.

In the Event trigger module, the procedure in section 14.10.1 doesn't explicitly say, if I am generating an interrupt every event to the PIE, do I have to clear the ETCLR.bit.INT in the interrupt in addition to clearing the PIEACK?  So by clearing the PIEACK it doesn't automatically clear the Event trigger flag?  Is this correct?  so we manually have to clear both?  correct?

Yes, I believe you have to clear the ET flag using ETCLR register.

Regards,
David

Hi Rob,

Yeah, you will need to clear both the PIE and the ePWM INT flag, and clearing via the PIE doesn't automatically clear the ePWM INT flag.

Unlike the SOC events, you definitely do need to acknowledge the ePWM INT flag before more events can be generated:

Thanks.

Going back to the first question, the problem was found to be that in table 14-7 the EPWM1 is tied to EXTSYNCIN1 and in figure 14-5 I was using the software SYNC, so the PHSEN enable was on, but because the default is that input 5 is connected to GPIO0 which also happens to be PWM output, the output state was affecting the sync...

Is there any way to 'DISABLE' this? ie: I want to enable the software sync, but not the hardwired sync. For now I reprogrammed the XBAR to an uused GPIO that I can externally tie low, but if I wanted to, is it possible to 'disable' this somehow? ie: force a low input on EPWMxSYNCI that doesn't tie up a GPIO externally?

Thanks.

3 additional questions:
1. Is there a way to ensure the DC module is 'inert' or disabled?
2. Is there a way to ensure the TZ module is 'inert' or disabled?
3. In figure 14-45 A issue I am noticing, is it appears that if I want to enable/disable the interrupt generation by use of ETSEL[INT], that if the timer is free running, then the counter appers to reach it's count, and stay there, so the 'instant' I enable the interrupts, and interrupt is generated. The question is, from looking at figure 14-45, how can I cleanly enable/disable the counter so that the instant I turn it on, it doesn't generate this first time interrupt?

I found the disable registers for the dead band and PC module, but couldn't find similar enable/disable registers for TZ and DC submodules, I just want to be sure they are disabled and won't produce any undesired results, what is the procedure to ensure they are disabled.