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F28M36P63C2: C28 EPI memory mapping and sizes

John Beard
Intellectual 390 points
Part Number: F28M36P63C2

I have an EPI bus set up with dual CS control. The CS0 device has 2 SRAM ICs, each with 2MB (2M * 8b) for a total of 4MB of storage. The M3 core can access all of this. The C28 core mapped region extends from 0x300000 to 0x340000, which is only 512kB (or 256 k-word). (Referring to table 18-10 in the TRM). Is that correct - the C28 can only access the lower addressed part of this memory, while M3 has full access?

Also the C28 mapping from 0x340000 to 0x380000 appears to alias back into the low memory, so read/write of 0x300000 and 0x340000 are the same. The M3 core seems to map correctly, with 0x60000000 and 0xA0000000 being independent and toggling the CS0/1 lines as expected. Is there an reason accesses to 0x340000 - 0x380000 might do this?

  • 0
    TI__Guru 62975 points

    John,

    The accessible range is meant to be the same between the M3 and C28.  The big difference is that the M3 is 8b-addressable, whereas the C28 is 16b-addressable.  I'm not sure if the C28 16b-addressability is contributing to some issues with your 8b SRAM.

    Can you attach a snippet of the schematic (or a text table) showing your EPI <-> SRAM connections?

    -Tommy

  • 0 in reply to tlee
    Intellectual 390 points

    Hi Tommy,

    The C28 address regions are only 0x40000 16-bit words per Chip Select (Table 18-10).  This is 256k words or 512k bytes. How can that be used to access all of 4 MB (2 * 2M * 8b)? That's a memory region of 0x200000 16-bit words, i.e. 8 times bigger. Table 18-10 does say only A0-A17 address lines are available, which fits the more limited size.

    The EPI <-> SRAM looks like the attached schematic (I forgot to mention the latched addressing).EPI_SRAM.pdf

  • 0 in reply to John Beard
    TI__Guru 62975 points

    John,

    You are correct.  I had a fuzzy mental moment.

    It does look like the EPI has asymmetric data access between the M3 and C28.  I think that the C28 may have been hard-coded for the quad-CS mode operation.  I will confirm this with a colleague who has more experience with EPI.

    If this is the case, the C28 would only be able to access the higher memory spaces by manually controlling the higher address pins through GPIO (rather than through EPI).

    -Tommy

  • 0 in reply to tlee
    TI__Guru** 115271 points

    Hi,

    Yes, as mentioned in document, C28 has access to only limited address range for each CSx space (A0 to A17). If you have data sharing between M3 and C28x and then max size is limited by C28x address space.

    Regards,

    Vivek Singh