Part Number: TMS320F28377D
Other Parts Discussed in Thread: CONTROLSUITE
Tool/software: Code Composer Studio
Hi I am trying to use F28377D's flashA , flashB , flashC parts as eeprom(I need to write and read some non-volatile data when software running and when software restart).I am using "\ti\controlSUITE\device_support\F2837xD\v210\F2837xD_examples_Dual\flash_programming\cpu01" as reference
project I write my codes over this project. I explained my problem steps below.
1 - I am writing flash when datas coming from serial port to flashA successfully(I combined flashA flashB and Flash C)
2 - I am cutting power off and then power on I am reading datas what I write to flashA with no poroblem
3 - Again I am writing flash when datas coming from serial port to flashA
4 - Again I am cutting power off and then power on I am reading datas what I write to flashA but datas are writen in step1 not step 3
I am using CCS 6.2.0 and my when my software start after hard reset it reads flash datas when datas coming from serial port it writes to flash.
I think I am writing succesfully only first time. What could be problem?
My linker file is
/*
//###########################################################################
// FILE: flash_programming_cpu1_FLASH.cmd
// TITLE: Linker Command File For all F28X7x devices
//###########################################################################
// $TI Release: F2837xD Support Library v210 $
// $Release Date: Tue Nov 1 14:46:15 CDT 2016 $
// $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
// The header linker files are found in <base>\F2837xD_headers\cmd
// For BIOS applications add: F28X7x_Headers_BIOS.cmd
// For nonBIOS applications add: F28X7x_Headers_nonBIOS.cmd
========================================================= */
/* Define the memory block start/length for the F28X7x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28M3Xx are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000122, length = 0x0002DE
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS03 : origin = 0x008000, length = 0x002000
/* RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800 */
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMGS14 : origin = 0x01A000, length = 0x001000
RAMGS15 : origin = 0x01B000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
// FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
// FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000
RAMGS13 : origin = 0x019000, length = 0x001000
FLASHA : origin = 0x080002, length = 0x005FFE //flashA,B,C combined
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHD PAGE = 0
.pinit : > FLASHD, PAGE = 0
.text : >> FLASHD | FLASHE PAGE = 0
codestart : > BEGIN PAGE = 0
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
GROUP
{
.TI.ramfunc
{ -l F021_API_F2837xD_FPU32.lib}
} LOAD = FLASHD,
RUN = RAMLS03,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0
#else
GROUP
{
ramfuncs
{ -l F021_API_F2837xD_FPU32.lib}
} LOAD = FLASHD,
RUN = RAMLS03,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0
#endif
#endif
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1 PAGE = 1
.esysmem : > RAMLS5 PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHF | FLASHG PAGE = 0
.switch : > FLASHD PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
Filter_RegsFile : > RAMGS0, PAGE = 1
SHARERAMGS0 : > RAMGS0, PAGE = 1
SHARERAMGS1 : > RAMGS1, PAGE = 1
/* Flash Programming Buffer */
BufferDataSection : > RAMD1, PAGE = 1, ALIGN(4)
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
My code flash routine
////////////////////////////////////////////////////////////////////////////////
void CallFlashAPI(uint32 flash_adress)
{
uint32 u32Index = 0;
uint16 i = 0;
Fapi_StatusType oReturnCheck;
volatile Fapi_FlashStatusType oFlashStatus;
Fapi_FlashStatusWordType oFlashStatusWord;
EALLOW;
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0x0;
oReturnCheck = Fapi_initializeAPI(F021_CPU0_BASE_ADDRESS, 200);
if(oReturnCheck != Fapi_Status_Success)
{
flash_error(oReturnCheck);
}
oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);
if(oReturnCheck != Fapi_Status_Success)
{
flash_error(oReturnCheck);
}
if (flash_write_command==1) //for write opration
{
for(i=0, u32Index = flash_adress;
(u32Index < (flash_adress + 48)) &&
(oReturnCheck == Fapi_Status_Success); i+= 8, u32Index+= 8)
{
oReturnCheck = Fapi_issueProgrammingCommand((uint32 *)u32Index,RBuffer+i,8,0,0,Fapi_DataOnly);
while(Fapi_checkFsmForReady() == Fapi_Status_FsmBusy);
if(oReturnCheck != Fapi_Status_Success)
{
flash_error(oReturnCheck);
}
oFlashStatus = Fapi_getFsmStatus();
oReturnCheck = Fapi_doVerify((uint32 *)u32Index,
4, RBuffer32+(i/2),
&oFlashStatusWord);
if(oReturnCheck != Fapi_Status_Success)
{
flash_error(oReturnCheck);
}
}
}
else if (flash_write_command==0) //for read opration
{
for(i=0, u32Index = flash_adress;
(u32Index < (flash_adress + 48)) &&
(oReturnCheck == Fapi_Status_Success); i+= 8, u32Index+= 8)
{
Fapi_doMarginRead((uint32 *)u32Index,(uint32 *)(RBuffer+i),8,Fapi_NormalRead);
//DELAY_US(10);
}
Read_Buffer_With_Integer_Values();
}
Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
EDIS;
ReleaseFlashPump();
flash_done();
}
////////////////////////////////////////////////////////////////////////////////