CCS/LAUNCHXL-F28377S: 2837x_rfft_adc_rt

You can tell if the sampling frequency is off by observing the input buffer right before the FFT is computed. So if i set a breakpoint at the point of calling the FFT,

    while(1){
        while(flagInputReady == 0){}; // Wait on ADC ISR to set the flag 
                                      // before proceeding
        RFFT_adc_f32(hnd_rfft_adc);   // Calculate real FFT (12-bit ADC input)<-------set breakpoint here
        flagInputReady = 0;           // Reset the flag

you can observe the sampled waveform in a graph. In CCS, in the debug perspective, go to Tools->Graph->Single Time, Set acquisition buffeer and Data size to 512, data type to unsigned 16 int, and start address to &RFFTin1Buff. Now if you are feeding in a 30KHz sine, and the sampling rate is exactly 100KHz, you should see about 3.3 (100/30) periods of the input. If not it means the sampling rate is off. We need to look at the frequency of EPWM1A ? I think its setup to output on GPIO0 - is it 100KHz?

I made a mistake in my earlier post. To figure out how many periods of the input you will capture in the input buffer for a given sampling rate is,

n_periods = N*(fi/fs) where N is the FFT size, fi the input frequency and fs the sampling frequency.

So for your case, N = 1024, fs = 100KHz (atleast that is what it should be) and lets take the first input fi = 5KHz

   n_periods  = 1024*(5e3/100e3) = 51.2 periods.

Now from your first image i count about 20 cycles in the first 196 points in the buffer so if i extend that to the full buffer that is about (20 * (1024/196)) ~ 104.49 periods in the full buffer. It looks like we are not sampling at 100KHz

  fs = N*(fi/n_periods) = 1024*(5e3/104.49) = 49KHZ.

Im going to assume we are sampling at 50KHz, which explains why everything input beyond 25KHz is wrong.

There is an issue with the setup of EPWM1A. Let me play around with the example a bit and figure out what the right configuration is.

Ok, I think i fixed it

In examples_setup.h, change the following lines

#define CPU_FRQ_200MHZ          1
#define ADC_SAMPLING_FREQ       100000.0L
#define EPWM_CLK                100000000UL // EPWM_CLK starts off SYSCLK/2
#define EPWM_CLKDIV             1           // TBCLK = SYSCLK/(2*2)
#define EPWM_HSPCLKDIV          4           //       = SYSCLK/(2*2*8) or EPWM_CLK/(2*8)
// desired freq 100KHz
#define EPWM1_PERIOD            EPWM_CLK/(2*8*100000UL)
#define EPWM1_DUTY_CYCLE        EPWM1_PERIOD/2UL
// desired freq 10KHz
#define EPWM2_PERIOD            (EPWM_CLK)/(2*8*10000UL)
#define EPWM2_DUTY_CYCLE        EPWM2_PERIOD/2UL

Then in examples_setup.c add these lines

void FPU_initEPWM(void)
{
    CpuSysRegs.PCLKCR2.bit.EPWM1             =1;  // Enable EPWM1 clocks
    CpuSysRegs.PCLKCR2.bit.EPWM2             =1;  // Enable EPWM1 clocks
    
    //Enable EPWM GPIOs
    InitEPwm1Gpio();
    InitEPwm2Gpio();
    
    EALLOW;
    // EPWM clock divider set to /2
    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1;                
    // Turn off the EPWM clock
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC       = 0;                
    // Disable SOC on A group
    EPwm1Regs.ETSEL.bit.SOCAEN             = 0;                
    // Select SOC on up-count
    EPwm1Regs.ETSEL.bit.SOCASEL            = 4;                
    // Generate pulse on 1st event
    EPwm1Regs.ETPS.bit.SOCAPRD             = 1;                
    // Set compare A value to 2000 counts
    EPwm1Regs.CMPA.bit.CMPA                = EPWM1_DUTY_CYCLE; 
    // Set period to 4000 counts
    EPwm1Regs.TBPRD                        = EPWM1_PERIOD;     
    // freeze counter
    EPwm1Regs.TBCTL.bit.CTRMODE            = 3;                
    //enable SOCA
    EPwm1Regs.ETSEL.bit.SOCAEN             = 1;
    EPwm1Regs.TBCTL.bit.CLKDIV             = EPWM_CLKDIV; //<------- Add line
    EPwm1Regs.TBCTL.bit.HSPCLKDIV          = EPWM_HSPCLKDIV;
    // Disable SOC on A group
    EPwm2Regs.ETSEL.bit.SOCAEN             = 0;                
    // Set compare A value to 10000 counts
    EPwm2Regs.CMPA.bit.CMPA                = EPWM2_DUTY_CYCLE; 
    // Set period to 20000 counts
    EPwm2Regs.TBPRD                        = EPWM2_PERIOD;     
    // freeze counter
    EPwm2Regs.TBCTL.bit.CTRMODE            = 3; 
    EPwm2Regs.TBCTL.bit.CLKDIV             = EPWM_CLKDIV; //<------- Add line
    EPwm2Regs.TBCTL.bit.HSPCLKDIV          = EPWM_HSPCLKDIV;
    // Clear PWM1A on Zero
    EPwm1Regs.AQCTLA.bit.CAU               = AQ_SET;           
    EPwm1Regs.AQCTLA.bit.PRD               = AQ_CLEAR;         
    // Clear PWM2A on Zero
    EPwm2Regs.AQCTLA.bit.CAU               = AQ_SET;           
    EPwm2Regs.AQCTLA.bit.PRD               = AQ_CLEAR;
    
    EDIS;
}