TMS320F28379D: SOCA on period match issue

Hello, I am just having an issue with an interrupt routine. I have setup an ePWM to trigger the SOC for the ADC which then sets the interupt when it is done.

void ConfigureADC(void)
{
EALLOW;

// ADC-A
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; // Set ADCCLK divider to /4
AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; // 12-bit resolution
AdcaRegs.ADCCTL2.bit.SIGNALMODE = 0; // Single-ended channel conversions (12-bit mode only)
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1; // Set pulse positions to late
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC

DELAY_US(1000); // Delay for 1ms to allow ADC time to power up

}


void SetupADCEpwm(void)
{
// Select the channels to convert and end of conversion flag
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // SOC0 will convert pin A0
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; // Sample window is 15 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 0x7; // Trigger on ePWM2 SOCA/C
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // End of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared

EDIS;
}

I also have configured the PWM as follows:

void InitEPwm2(void)
{
EALLOW;
// Assumes ePWM clock is already enabled
EPwm2Regs.TBCTL.bit.CTRMODE = 3; // Freeze counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 1; // TBCLK pre-scaler = /2
EPwm2Regs.TBPRD = period2; // Set period to 50000 counts (2kHz)
EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
EPwm2Regs.ETSEL.bit.SOCASEL = 2; // Select SOCA on period match
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA
EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; // SYNC output
EPwm2Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm2Regs.TBCTL.bit.PHSDIR = 1; // set phase direction
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0

EDIS;
}

So my issue is that when EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0 the code WILL enter my interrupt service routine and when it = 1 the code WILL NOT enter the ISR.  Any help is much appreciated