Other Parts Discussed in Thread: CONTROLSUITE
Hello TI community,
I was wondering how exactly does the FIFO work for the SPI. I am looking at the example code in controlSUITE. I understand that writing the spi transfer buffer will write to the fifo. The fifo then writes to the SPI shift register, sending MSB bits out first. Let's say I do three write operations to the transfer buffer using a for loop such as:
for(i=0; i<3; i++)
{
spi_xmit(SPI, sdata[i]);
}
given
void spi_xmit(volatile struct SPI_REGS *SPI, Uint16 a)
{
(*SPI).SPITXBUF = a;
}
Will the chip understand that after each write statement to write to the FIFO in time for the next transfer function write? Or will this cause issues in timing?
