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TMS320F28375S: Confirm the EMIF specification

Kaka
Guru 24520 points
Part Number: TMS320F28375S
Other Parts Discussed in Thread: C2000WARE

HI TI Experts,

Please let me confirm the following question.

[Question.1]
Will the data bus of EMIF1 be Low when the F28375S does not access any CS region?

[Question.2]
Does the data bus of EMIF2 continue to hold the latest writing value?

-> My customer said that if the SDRAM of connecting to EMIF2 is write the value via CCS, it could read the latest writing value.

Best regards.
Kaka

  • 0
    TI__Guru** 116021 points

    Hi Kaka,

    Will the data bus of EMIF1 be Low when the F28375S does not access any CS region?

    Data bus is invalid. User should not assume any value on data bus when there is no valid access.

    Does the data bus of EMIF2 continue to hold the latest writing value?

    Yes. that is correct. Please refer section "25.3.7 Data Bus Parking" of TRM.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Guru 24520 points
    Hi Vivek,

    Thank you for your response.
    Please let me confirm the following question in addition to above questions.
    [Question]
    My customer concerned that the EMIF data bus lines were "Low" even though there are pull-up registers on those lines when DSP was stopped by CCS. Does this behavior correct as device operation?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116021 points
    Hi Kaka,

    Data pins are in output mode unless there is READ hence pull will not take any effect.

    Regards,

    Vivek Singh
  • 0 in reply to Vivek Singh
    Guru 24520 points
    Hi Vivek,

    Thank you for your response.
    I would like to know the reason why the device will be "Low" when the device was stopped by CCS. Would you please explain it in detail?
    Does the "Output mode" mean that the device will be enabled the "Data Bus Parking"?

    Also, when my customer tried to do the device was set the EMIF pins as GPIO, the EMIF data bus lines were "High" status.
    So, it seems that the "Low" status on bus lines was drive by device. what do you think about?
    And there were noise on those line. They understand that this settings is incorrect, but they also would like to know the reason why there were noise on EMIF bus lines.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116021 points
    Hi Kaka,

    In GPIO mode, by default pins are in input mode (tri-state from device) hence pins will remain in a state based on external pulls/driver. As soon as pins are switched to EMIF mode, it becomes output and in that case some value will be driven on the pin. In starting these could be '0' because there was no access. Even in GPIO mode, if you change the direction of the pin to output mode, pin will be driven '0' by default.

    I am not sure about noise. This could be because of board issues.

    Regards,
    Vivek Singh
  • 0 in reply to Vivek Singh
    Guru 24520 points
    Hi Vivek,

    Thank you for your response.
    By the way, would you please provide your comments for the following my question?
    > I would like to know the reason why the device will be "Low" when the device was stopped by CCS. Would you please explain it in detail?
    >Does the "Output mode" mean that the device will be enabled the "Data Bus Parking"?
    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116021 points

    Hi Kaka,

    > I would like to know the reason why the device will be "Low" when the device was stopped by CCS. Would you please explain it in detail?

    I may not be understanding this question properly. Are you saying in middle of EMIF transaction if CPU is halted by debugger, all the EMIF data lines goes low?

    >Does the "Output mode" mean that the device will be enabled the "Data Bus Parking"?

    Output mode means data lines will be driven with active value. Data Bus Parking is always enable.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Guru 24520 points
    Hi Vivek,

    Thank you for your response.
    > Are you saying in middle of EMIF transaction if CPU is halted by debugger, all the EMIF data lines goes low?
    [Kaka]
    Yes, your understanding is correct. So, I would like to know the reason why the EMIF data lines go low.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 24520 points
    Hi Vivek,

    I got more feedback from them.
    The EMIF data lines will go Low when the device is suspended even though the latest value was "1" for data bus lines.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 24520 points
    HI Vivek,

    Would you please provide your comments?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116021 points
    I may have to check with design team on this. Will get back to you in 1-2 days.

    Vivek Singh
  • 0 in reply to Vivek Singh
    Guru 24520 points
    HI Vivek,

    Thank you for your response. I got it. I am waiting for your feedback.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116021 points

    Hi Kaka,

    I tried this on my setup and I do not see data pins going low when CPU is halted. Is it possible to get the sample code from customer which I can run on my setup to check this?

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Guru 24520 points
    Hi Vivek

    I could reproduce this phenomenon by using the sample code of "emif1_16bit_asram_cpu01" in C2000Ware with using launchxl-f28377s.
    Please use this code and confirm the pin status of EMIF data lines.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116021 points

    Hi Kaka,

    I have used this example as well as SDRAM example and do not see this. Also customer is using SDRAM or ASRAM?

    It could be that I am not following correct sequence. Can you write the exact steps and observations to reproduce this issue?

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Guru 24520 points

    Hi Vivek,

    They have used the ASRAM.

    Did you do the pull-up for EMIF data line?
    Just in case, I summary the method to reproduce as below.
    1. Pull-up the EMIF data line which there is on LaunchPad booster header.
    2. Run the Example code until initialization of EMIF pins.
    3. Check the pin status.
    -> You will be able to confirm those pins were "Low" status when suspend the program.

    Best regards.
    Kaka

  • 0 in reply to Kaka
    TI__Guru** 116021 points

    Hi Kaka,

    After EMIF initialization, data pins will be driven LOW. That is expected output.

    Vivek Singh

  • 0 in reply to Vivek Singh
    Guru 24520 points

    No.... I do not understand that why we could confirm the high  status on those pins when CPU is running even though data pins will be driven LOW after initialization.. The EMIF pins status will be low when the CPU output data or the CPU was suspended. So, you wil be able to confirm this phenomenon after finished this sample code.
    Please re-check the following method.

    1. Pull-up the EMIF data line which there is on LaunchPad booster header.
    2. Run the Example code until finishing program.
    3. Check the pin status.
    4. Check the pin status when CPU suspends

    I would like to know why this EMIF data pins will be low when the CPU was suspended.
    Regards.
    Kaka

  • 0 in reply to Kaka
    TI__Guru** 116021 points
    Kaka,

    How are you checking the status of pins in step 3? Are you putting while(1) loop after EMIF initialization? What happens if you suspend the CPU after a write. E.g write data 0xFFFF to external memory and then suspend the CPU and check the value on data pins.

    Vivek Singh
  • 0 in reply to Vivek Singh
    Guru 24520 points
    Hi,

    Yes, I added the while loop to sample code. The pin was low status even though writing the 0xFFFFFFFF. i.e. I changed the value form to "mem_wds=0x01234567" to "mem_wds = 0xFFFFFFFF"
    Can you reproduce this phenomenon?
    We need to answer to my customer ASAP.... because it takes too long time to answer....

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 24520 points
    Hi

    I could not reproduce this phenomenon....
    I will retried to do.

    Best regards.
    KAka
  • 0 in reply to Kaka
    Guru 24520 points

    Hi
    I could reproduce. When finished the program, the data line was low.
    Also when suspend the program at 112 line, the data line was low.
    If change the pin mux from EMIF to GPIO, the data line was High status.

    * I checked this phenomenon at GPIO 73pin.


    Best regards.
    Kaka

  • 0 in reply to Kaka
    Guru 24520 points
    Hi Vivek

    Do you have any update?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116021 points

    Kaka,

    In last post you mentioned this -

    "When finished the program, the data line was low."

    "Also when suspend the program at 112 line, the data line was low."

    So in both condition data lines were low. In case of GPIO, by default pins are in INPUT mode (tri-stated) hence pins will be in HIGH state due to external pull-up.

    As I mentioned earlier, CPU suspend has no impact on EMIF data lines and I have checked this on board as well.

    Also is this issue specific to GPIO73 or all GPIO pins with EMIF data function.

    Do you have contact with any FAE (field application engineer) in your region? If yes then talk to him about this issue and we can setup a webex session to look into this.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Guru 24520 points
    Hi vivik,

    My customer said that this phenomenon was happened on all GPIO pins. My customer's question is that why those pins will be low when the CPU suspend. I understand that this phenomenon does not impact for device operation but they would like to know that reason.

    No. This customer is the unsigned customer. So we could not get your local FAE cooperation.

    Best regards.
    Kaka
  • 0 in reply to Kaka
    Guru 24520 points
    Hi Vivik,

    Would you please provide your comments if possible?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116021 points
    Hi Kaka,

    As I mentioned, I am not able to reproduce this issue on my setup and from spec point of view we do not see any dependency on CPU suspend for GPIO state. That is why I was asking to contact FAE so that we can setup a call/webex to look into this further.

    Vivek Singh