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TMS320F28377S: Flash prefetch protected by ECC?

Part Number: TMS320F28377S


It is not clear from the technical reference manual (SPRUHX5D) for the TMS320F2837xS if the flash prefetch mechanism for the instruction buffer described in section 2.12.8.1.2 provides any memory protection such as ECC or parity.  I would like the utilize the prefetch and in the past we've disabled such a feature because of a concern about susceptibility to a single event upset. 

Sorry if this question has been answered already, I was unable to find any previous question on this topic.

  • Hi Jordan,

    All of Flash memory including OTP is ECC protected, only exception is the OTP link pointer locations.

    Also, as described in section 2.12.8.1.2 - "If the prefetch mechanism is enabled, then the last row of 128 bits in the bank should not be used, because the prefetch logic which does a look-ahead prefetch, will try to fetch from outside the bank and would result in an ECC error".

    Hope this helps, let us know if you have any more questions.

    Regards,
    Nirav
  • Jordan,

    Flash contents are verified for ECC correctness before they enter the prefetch buffer. But there is no ECC or parity supported on the prefetch buffer itself.

    I will file a ticket to mention this detail in TRM if it is not already mentioned in there.

    Thanks and regards,
    Vamsi
  • Thank you Vasmi, this answer addresses my question.

    The TRM does not state if there is ECC or parity protection in the two sequential instruction buffers or the singe data cache when the prefetch is enabled.
  • Jordan,

    Same thing with the datacache. ECC is checked for the Flash content before it enters in to data cache but there is no ECC support on the data cache itself.

    I filed a ticket to document the same.

    Thanks and regards,
    Vamsi