• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 84 subscribers
  • Views 1433 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

F28M36P63C2: RAM/Flash error rates

Cedric 40627
Expert 1580 points
Part Number: F28M36P63C2


Hi,

I am working on implementing safeguards regarding memory failure on a Concerto device. I see that you have several ECC registers to take care of that...  one can trigger an interruption based on a counter threshold defined by the user.

I wanted to know if TI had collected any data regarding the error rates of the Flash and RAM when these two are used intensively... so I can have a bulk part idea of an acceptable threshold value.

Thanks.

  • 0
    TI__Guru* 87155 points
    Cedric,

    Flash technology used in this device is very reliable. Based on the field empirical data, no fails are reported for this concern. You should be able to go with a threshold of 1.

    Note that there is an errata (Advisory C28x Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error
    Interrupt Service Routine) that requires you to set the threshold to a value greater than or equal to 1.

    I will ask our RAM expert to take a look at this.

    Thanks and regards,
    Vamsi
  • 0 in reply to Vamsi Gudivada
    Expert 1580 points

    Hi Vamsi,

    Thanks for FLASH details and the reference to the errata. To give you a feel of RAM use, I execute a motor control loop routines from RAM at ~60KHz which use approximately 85% of CPU time. 

    Thanks for checking with RAM experts.

  • 0 in reply to Cedric 40627
    Expert 1580 points
    Any update on that question ?
  • 0 in reply to Cedric 40627
    TI__Guru* 87155 points
    Cedric,

    I will remind our RAM expert to look in to this.

    Thanks and regards,
    Vamsi
  • 0 in reply to Vamsi Gudivada
    TI__Expert 5800 points

    Cedric,

    The RAM is intrinsically very reliable and will not have any data errors when the device is used within the Recommended Operating Conditions.

    There are generally two types of errors which could occur, and both have a very low occurrence rate.

    1) SER (soft error rate), usually from cosmic particles.  These are extremely rare but could impact multiple bits in different RAM words, maybe up to 3-4 for a single event.  This is the primary purpose of the ECC protection on the device. 

    2) Latent defect in the device.  This is also very rare but is a possibility.  If a RAM bit has a defect causing it to flip, this will occur regularly over and over again at the same location.  ECC will typically correct this but it is a case where you may want to take the unit out of service.

    So generally I would recommend setting a limit of >10 for ECC errors before taking action.  This will ignore SER errors but flag any repeatable device issue.

    Best regards,

    Jason

  • 0 in reply to Jason Whiles
    Expert 1580 points
    Thank you Jason. This is the kind of rationale I was looking for.