Hi TIers,
I am working on implementing a routine to verify that the ECC module of the RAM is working properly. I encountering a problem with the single corrected error counter which doesn't increment... Could you take a look at my code below and advise ? From the watch window, CCETRES is set correctly to 4, gRAMTestL0..3 are correctly bit-flipped then corrected back to 0 when test mode is disabled.
#define DEFAULT_ECC_ERROR_THRESHOLD 4
#pragma DATA_SECTION(gRAMTestL0, "RAMTestL0File");
volatile uint32_t gRAMTestL0;
#pragma DATA_SECTION(gRAMTestL1, "RAMTestL1File");
volatile uint32_t gRAMTestL1;
#pragma DATA_SECTION(gRAMTestL2, "RAMTestL2File");
volatile uint32_t gRAMTestL2;
#pragma DATA_SECTION(gRAMTestL3, "RAMTestL3File");
volatile uint32_t gRAMTestL3;
void enableRamECC(){
EALLOW;
RAMErrRegs.CCETRES = DEFAULT_ECC_ERROR_THRESHOLD; // Threshold of error
RAMErrRegs.CCEIE.bit.C28CEIE = 1; // Correctable error interrupt is generated when the CCEFLG flag is set.
EDIS;
}
systemControlError_t RAMSelfTest(void){
enableRamECC();
EALLOW;
//Initialize RAM for self-testing. Write 0x0 data and respective ECC/parity bits accordingly.
RAMRegs.CLxRTESTINIT1.bit.RAMINIT_L0 = 1;
while(!RAMRegs.CLxRINITDONE.bit.RAMINITDONE_L0);
RAMRegs.CLxRTESTINIT1.bit.RAMINIT_L1 = 1;
while(!RAMRegs.CLxRINITDONE.bit.RAMINITDONE_L1);
RAMRegs.CLxRTESTINIT1.bit.RAMINIT_L2 = 1;
while(!RAMRegs.CLxRINITDONE.bit.RAMINITDONE_L2);
RAMRegs.CLxRTESTINIT1.bit.RAMINIT_L3 = 1;
while(!RAMRegs.CLxRINITDONE.bit.RAMINITDONE_L3);
EDIS;
// ECC error counter should be 0
if(RAMErrRegs.CCECNTR){
return ECC_RAM_ERRCNTR_FAILURE;
}
// ECC error flag should be cleared.
if(RAMErrRegs.CCEFLG.bit.C28CEFLAG){
return ECC_RAM_CEFLAG_FAILURE;
}
// Enable RAM Test mode (section 5.1.1.8) , disable parity/ECC test
EALLOW;
RAMRegs.CLxRTESTINIT1.bit.ECCPARTEST_L0 = 1;
RAMRegs.CLxRTESTINIT1.bit.ECCPARTEST_L1 = 1;
RAMRegs.CLxRTESTINIT1.bit.ECCPARTEST_L2 = 1;
RAMRegs.CLxRTESTINIT1.bit.ECCPARTEST_L3 = 1;
EDIS;
// prepare errors... flip one bit to create correctable errors.
// In RAM test mode, only the data is updated, not the ECC.
// Therefore when test mode is turned off, ECC module should capture these errors.
gRAMTestL0 ^= 0x1;
gRAMTestL1 ^= 0x1;
gRAMTestL2 ^= 0x1;
gRAMTestL3 ^= 0x1;
EALLOW;
RAMRegs.CLxRTESTINIT1.bit.ECCPARTEST_L0 = 0;
RAMRegs.CLxRTESTINIT1.bit.ECCPARTEST_L1 = 0;
RAMRegs.CLxRTESTINIT1.bit.ECCPARTEST_L2 = 0;
RAMRegs.CLxRTESTINIT1.bit.ECCPARTEST_L3 = 0;
EDIS;
// Clear CCEFLG
EALLOW;
RAMErrRegs.CCECLR.bit.C28CECLR = 1;
EDIS;
if(gRAMTestL0 || gRAMTestL1 || gRAMTestL2 || gRAMTestL3){
return ECC_RAM_FAILURE;
}
return NO_ERROR;
}
My command file:
RAMTestL0File : > RAML0, PAGE = 0
RAMTestL1File : > RAML1, PAGE = 0
RAMTestL2File : > RAML2, PAGE = 0
RAMTestL3File : > RAML3, PAGE = 0
... which effectively position the variable at expected memory banks (verified with memory browser).
