Part Number: F28M36P63C2
Hi,
I am working on implementing a ECC self-test routine for my concerto device. I followed the instructions detailed in the data sheet but I have a problem when entering the interrupt "single flash error". In step-by-step debug, the program never enter the ISR even with PIEFR12 being correctly set to 2 when the ecc test mode is enabled. The code execution stays stuck in unconditional loop. Please see code attached and advise.
#pragma DATA_SECTION(gFlashAECCTest, "FlashAECCTestFile");
uint32_t gFlashAECCTest;
#pragma DATA_SECTION(gFlashBECCTest, "FlashBECCTestFile");
uint32_t gFlashBECCTest;
systemControlError_t testFlashECCLogic(const uint32_t * address, const eccFlashTestType_t testType){
char ecc;
/* guidelines detailed in section 5.3.10.3 */
EALLOW;
ecc = Fapi_calculateEcc((uint32_t)(address) << 1, (uint64) 0x0000000000000000);
FlashEccRegs.ERR_THRESHOLD.bit.ERR_THRESHOLD = 1; /* cannot be 0 - see device errata */
FlashEccRegs.FADDR_TEST.bit.ADDR = (testType == TEST_ADDRESS_SINGLE_BIT) ? (uint32_t)(address) ^ 0x1 : (uint32_t)(address);
FlashEccRegs.FDATAH_TEST = (testType == TEST_DATAH_SINGLE_BIT) ? 0x00000001 : 0x00000000;
FlashEccRegs.FDATAL_TEST = (testType == TEST_DATAL_SINGLE_BIT) ? 0x00000001 : 0x00000000;
FlashEccRegs.FECC_TEST.bit.ECC = (testType == TEST_ECC_SINGLE_BIT) ? ecc ^ 0x1 : ecc;
FlashEccRegs.FECC_CTRL.bit.ECC_SELECT = (testType == TEST_DATAL_SINGLE_BIT) ? 0 : 1;
FlashEccRegs.FECC_CTRL.bit.ECC_TEST_EN = 1;
EDIS;
asm(" NOP");
EALLOW;
FlashEccRegs.FECC_CTRL.bit.ECC_TEST_EN = 0;
FlashEccRegs.ERR_CNT.bit.ERR_CNT = 0;
EDIS;
return SYS_CTL_NO_ERROR;
}
systemControlError_t testFlashBank(const uint32_t * address){
systemControlError_t ret;
if((ret = testFlashECCLogic(address, TEST_ADDRESS_SINGLE_BIT)) < 0) return ret;
if((ret = testFlashECCLogic(address, TEST_DATAL_SINGLE_BIT)) < 0) return ret;
if((ret = testFlashECCLogic(address, TEST_DATAH_SINGLE_BIT)) < 0) return ret;
if((ret = testFlashECCLogic(address, TEST_ECC_SINGLE_BIT)) < 0) return ret;
return SYS_CTL_NO_ERROR;
}
systemControlError_t flashSelfTest(void){
systemControlError_t ret;
enableFlashECC();
if((ret = testFlashBank(&gFlashAECCTest)) < 0) return ret;
if((ret = testFlashBank(&gFlashBECCTest)) < 0) return ret;
return SYS_CTL_NO_ERROR;
}
systemControlError_t initializeECC(void){
systemControlError_t err;
/* Direct interrupt signals to ISR */
EALLOW;
PieVectTable.CFLSINGERR = &flashSingleError;
PieVectTable.CRAMSINGERR = &ramSingleError;
EDIS;
// Enable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
PieCtrlRegs.PIEIER12.bit.INTx2 = 1; // Enable PIE Group 12 INT2 (flash single error)
PieCtrlRegs.PIEIER12.bit.INTx4 = 1; // Enable PIE Group 12 INT4 (ram single error)
PieCtrlRegs.PIEACK.all = M_INT12 ; // Enable nesting in the PIE
asm(" NOP"); // Wait for PIEACK to exit the pipeline Ref. Usage note errata sheet SPRZ272H
IER |= M_INT12;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// First we verify that the ECC modules "SECDED" work properly
// We put the RAM in test mode and inject some error...
// if((err = RAMECCSelfTest()) < 0){
// DINT; // Disable Global interrupt INTM
// DRTM; // Disable Global realtime interrupt DBGM
// return err;
// }
if((err = flashSelfTest()) < 0){
DINT; // Disable Global interrupt INTM
DRTM; // Disable Global realtime interrupt DBGM
return err;
}
DINT; // Disable Global interrupt INTM
DRTM; // Disable Global realtime interrupt DBGM
return SYS_CTL_NO_ERROR;
}
interrupt void flashSingleError(void){
EALLOW;
gFlashECCSingleErrorAddress = FlashEccRegs.SINGLE_ERR_ADDR;
gFlashECCErrorStatus = FlashEccRegs.ERR_STATUS.all;
gFlashECCErrorPositionReg = FlashEccRegs.ERR_POS.all;
gFlashCorrectedErrorCounter++;
FlashEccRegs.FECC_CTRL.bit.ECC_TEST_EN = 0;
EDIS;
}
My cmd file:
FlashAECCTestFile : > FLASHA, PAGE = 0, ALIGN(4)
FlashBECCTestFile : > FLASHB, PAGE = 0, ALIGN(4)
