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CCS/TMS320F28069: 1MHz ADC sampling frequency question

WANG NING
Intellectual 490 points
Part Number: TMS320F28069


Tool/software: Code Composer Studio

I am using 28069 controlSTICK to implement a simple oscilloscope with 2 ADC channel both at 1MHz sampling rate.

ADCCLK is 45MHz

ADCINA2 and ADCINB2 sample sequentially in continuous mode, SOC0/1 triggered by ADCINT1, EOC0 triggers ADCINT1,EOC1 triggers ADCINT2

so I think the following setup should give 1MHz for each channel:  45MHz/(6+16)/2 = 1.022MHz

    EALLOW;
    AdcRegs.ADCCTL2.bit.CLKDIV2EN = 1;
    AdcRegs.ADCCTL2.bit.CLKDIV4EN = 0;             //ADCCLK=SYSCLK/2
    DELAY_US(ADC_usDELAY);                                 // Delay before converting ADC channels
    AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1;        // late interrupt pulse
    AdcRegs.INTSEL1N2.bit.INT1E     = 1;                  // Enabled ADCINT1
    AdcRegs.INTSEL1N2.bit.INT1CONT  = 1;            // Enable ADCINT1 Continuous mode
    AdcRegs.INTSEL1N2.bit.INT2E     = 1;                  // Enabled ADCINT2
    AdcRegs.INTSEL1N2.bit.INT2CONT  = 1;            // Enable ADCINT2 Continuous mode
    AdcRegs.INTSEL1N2.bit.INT1SEL   = 0;               // setup EOC0 to trigger ADCINT1 to fire
    AdcRegs.INTSEL1N2.bit.INT2SEL   = 1;               // setup EOC1 to trigger ADCINT2 to fire
    AdcRegs.ADCSOC0CTL.bit.CHSEL    = 2;           // set SOC0 channel select to ADCINA2
    AdcRegs.ADCSOC1CTL.bit.CHSEL    = 10;         // set SOC1 channel select to ADCINB2
    AdcRegs.ADCINTSOCSEL1.bit.SOC0 = 1;           // ADCINT1 will trigger SOC0
    AdcRegs.ADCINTSOCSEL1.bit.SOC1 = 1;           // ADCINT1 will trigger SOC1
    AdcRegs.ADCSOC0CTL.bit.ACQPS    = 15;         // set SOC0 S/H Window to 16 ADC Clock Cycles, (15 ACQPS plus 1)
    AdcRegs.ADCSOC1CTL.bit.ACQPS    = 15;         // set SOC1 S/H Window to 16 ADC Clock Cycles, (15 ACQPS plus 1)
    EDIS;

So if I display 100 points when measuring a 10KHz sine signal, it should give a full period of sine wave. But I am getting 5 here, which means the sampling rate is about 200KHz.

Can somebody point out any issue in my code or anything I missed? 

  • 0
    TI__Guru 54295 points
    Hello,

    I think maybe you have some register configurations leftover by the AdcOffsetSelfCal() function (which I'm assuming you're calling somewhere earlier in the application?) that's causing you to trigger more SOCs than intended. Try clearing out the ADCINTSOCSEL1 and ADCINTSOCSEL2 registers before you configure ADCINTSOCSEL1 for SOC0 and SOC1.

    Whitney
  • 0 in reply to Whitney Dewey
    Intellectual 490 points
    Thank you very much! problem solved.

    One more question, in 2806x doc, ADCCLK is half of sysclk at 45MHz, maxium by setting CLKDIV2EN = 1 and CLKDIV4EN = 0. I tried both set to zero, which gives 90MHz ADCCLK. And I can see the sampling rate doubles. So ADCCLK can be configured at 90MHz maximum. Is it correct?? why the spec says 45MHz
  • 0 in reply to WANG NING
    TI__Guru 54295 points

    The datasheet is correct when it says that the max is 45MHz. I don't personally know the details of how they determined to be the maximum in their testing and what specifically goes wrong at higher speeds. Stick to 45MHz to avoid possible bad behavior.

    Whitney

  • 0 in reply to Whitney Dewey
    TI__Guru 62975 points
    Wang Ning,

    The ADC performance falls outside of datasheet specs when the frequency is above 45MHz.

    -Tommy
  • 0 in reply to tlee
    Intellectual 490 points
    Hi Tommy,

    In terms of ADC performance, I think if I give enough time for the S/H window, it should be OK?
    for example, under 45MHz ADCCLK, the datasheet says the S/H window is at least 7 cycles. so if I config the ADCCLK at 90MHz, then I set S/H window for over 14 cycles. Can I suppose so?
    The reason I am trying to do this is that I really want to have a perfect 1MHz SR, with 45MHz ADCCLK I cannot get this.
    Another question, can I change the config of ADC (trig source, trig mode etc.) when it is running? Or do I have to disable and enable it again during re-config?
  • 0 in reply to WANG NING
    TI__Guru 62975 points
    Wang Ning,

    The ADC state machine has not been approved for 90MHz operation. That is the reason that the module clock needs to be limited to 45MHz -- it is not the ACQPS window that is the concern.

    You can use different SYSCLK frequencies to try to achieve your desired sampling rate. For example, running the device at 60MHz, CLKDIV2, NONOVERLAP, and ACQPS=16 should give you 1MSPS.

    There's also the approach of using the EPWM to trigger conversions at a periodic 1MHz rate rather than using the ADC in continuous sampling mode.

    -Tommy