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TMS320F28377D: ADC sampling rate

Himanshu Chaudhary
Prodigy 130 points
Part Number: TMS320F28377D


Can someone please specify the maximum ADC sampling rate  of this device which includes both hardware latency(Conversion cycles etc.) and software latency (reading ADC value etc.). Kindly specify the sampling rate in MSPS.

  • 0
    Guru 192875 points
    Hi Himanshu,

    The Product page clearly mentions : ADC16/12 [x4]: 1-S/H, 1.1/3.5-MSPS

    Regards,
    Gautam
  • 0 in reply to Gautam Iyer
    TI__Guru 60865 points
    Hi Himanshu,

    To elaborate just a little bit:

    After results are latched into RAM, there are no wait-states to access the result registers; they can be read in a single CPU cycle. The registers are also mapped to both CPUs, both CLAs, and both DMAs so you have plenty of options for dealing with samples, even if they are coming in at a high rate. There is also minimal pipe lining in the ADC on this device, so the sample-to-output latency is within a cycle or two of 1 / sample rate.

    Since the CPUs are 200MHz and the maximum sample rate is 3.5MSPS you will have ~57 cycles to deal with each set of 4 conversions. This is actually enough time to take an interrupt and do a couple operations (but at that rate I'm not sure I'd recommend triggering an ISR after the end of each group of samples).