• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 82 subscribers
  • Views 1091 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28377D: CLA access time to GPIO Data Register

Himanshu Chaudhary
Prodigy 130 points
Part Number: TMS320F28377D

I have observed that accessing GPYDAT register in CPU1 is a lot faster than CPU1.CLA. Although bot of them share the same bus for reading. Can someone suggest what is the reason behind this.

  • 0
    TI__Guru** 113875 points
    Himanshu,

    How much difference (number of cycles) you are observing? Also how are you measuring this? Have you checked the assembly file for both the codes?

    Vivek Singh
  • 0 in reply to Vivek Singh
    Prodigy 130 points
    Vivek
    CLA is taking nearly 8 clock cycles more to read GPIO port than CPU. I measured this using by generating some signal after reading the data port. Generation of that signal is taking same time in both CPU and CLA (I have checked that). So only difference in time is due to reading the GPIO PORT. Maybe CLA and CPU have different architectures and pipeline stages to fetch data from a register. But I am not sure about this.
  • 0 in reply to Himanshu Chaudhary
    TI__Guru** 113875 points
    Himanshu,

    Architecture of CLA and CPU is little different but should not have 8 cycle difference unless there is pipeline flush in one case but not in other. Do you have sample code which you can pass and I can check.

    Vivek Singh