CCS/TMS320F2812: How to set FIFO register

Michiel van Rijnbach81

Part Number: TMS320F2812

Tool/software: Code Composer Studio

Hi,

I've just started programming the TMS320F2812 and I was looking through the example file Example_281xSciFFDLB_int.c for programming the serial communication interface with FIFO buffers and interrupts. In the two functions scia_fifo_init() and scib_fifo_init() the communication is initialized by setting several registers. I don't understand why the FIFO transmit register SCIFFTX gets the value 0xC028. According to the reference guide (SPRU051D) an interrupt is generated when the status bits (TXFFST) are equal or less than the interrupt level bits (TXFFIL). I assume the status bits are updated dynamically depending on the number of words in the FIFO. However, in the case of the value 0xC028 the status bits are 00000 and the interrupt level bits are 01000, so the status bits are equal or less than the interrupt level bits. Does this mean that there are continuously interrupts, until there are 01000= 8 words in the FIFO buffer? Furthermore, I assume these are not software interrupts, but they are taken care of by the hardware. I would appreciate it if anybody could provide me with some answers. I didn't find too much information about this in the reference guide.

Best regards, Michiel van Rijnbach.

over 8 years ago

0 Vincent Rodriguez over 8 years ago

TI__Mastermind 28285 points

Hey Michiel,

The way it works is when TXFFST <= TXFFIL, and interrupt will be generated. so if you never filled the FIFO, and serviced the interrupt but didn't disable it, this interrupt would constantly be going off.

The example is an endless transmit example. you can fill the FIFO with 16 words, and when the TXFFST drops below 8, and interrupt is generated, and you can add 8 more words.

You can do this forever, like the example, or you can stop it by disabling the TX interrupt until you are ready to transmit.

Hope that helps!

Vince Rodriguez

0 Michiel van Rijnbach81 over 8 years ago in reply to Vincent Rodriguez

Intellectual 330 points

Thank you Vince, that's exactly what I needed to know. I was kinda assuming it worked that way, but couldn't find the details in the reference guide. I was wondering what use it is to write the status bits in the FIFO register, but obviously they are being updated by the hardware. Are these interrupts generated every clock cycle?

Best regards, Michiel.

0 Vincent Rodriguez over 8 years ago in reply to Michiel van Rijnbach81

TI__Mastermind 28285 points

The status bits are read only, so when you write to the entire register, you will only change the bits that are writable.

For the interrupt, it will be generated when the above condition is met, and the interrupt flag has been cleared.

Thanks,

Vince Rodriguez

0 Michiel van Rijnbach81 over 8 years ago in reply to Vincent Rodriguez

Intellectual 330 points

Thank you for your clarifications.

Best regards, Michiel.

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CCS/TMS320F2812: How to set FIFO register