Other Parts Discussed in Thread: CONTROLSUITE
Tool/software: TI C/C++ Compiler
I didn't realize until I went to convert my project from the F28377S to the F28379D all of the hoops that are required to load and run code for 2 CPUs. One of the biggest surprises was that two projects are required, which are compiled and linked separately - which will make development and testing much slower. Now, I understand that each CPU has it's own M0/1, D0/1, and LS0-5 RAM, and that they share GS0-15. Since GS0-3 fall under the 64k limit, I believe, they can contain program data. What I'm curious about is, besides (the obvious) including the same shared source code in both projects, how does one make sure that shared functions and/or data occupy the same locations in the GS RAM, so that both CPUs can point to them? Regarding the shared data, I'm thinking about readonly constants - I would obviously use the IPC RAM to share information between the two CPUs.
(as an aside, the TI compiler makes it simple to program for 1 CPU, and it surely seems that all of the steps for loading for two could be automated by the IDE/compiler - including having shared and complementary memory cmd files, and common includes).