I have an application for using SRAM as follows:
1. 1M x 16 asynchronous SRAM (Cypress CY7C1061GN30-10, 
) using EMIF1_CS2_N (2Mx16 space, 0x0010 0000 to 0x002F FFFF) in normal mode.
2. 256k X 16 asynchronous NVSRAM (Cypress CY14B104NA-ZS20, ) using EMIF_CS3_N (512Kx16 space, 0x0030 0000 to 0x0037 FFFF) in normal mode. This part functions as a standard SRAM which automatically stores the data to non-volatile elements upon loss of power or SW command.
When selecting EMIF interface in pinmux tool, none of the EMDQMx pins are commissioned, despite the fact that the TRM suggests using those for selecting between low and high bytes. If we follow the TRM however, we end up not having enough address pins available.
Do we have an example application for regular SRAM's we can use? Can you explain the discrepancies we found?
Thank you!
