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RE: TMS320F28335 - SPI on McBSP read word length

Lukas Brzyszkiewicz
Intellectual 335 points

Bump this question.

I have same problem - in documentation (Delfino F28335 McBSP.) site 61 - XFRLEN1 and RFRLEN1 in Clock Stop Mode must use frame length = 1. But with this setting I have undesirable Chip Select clocking.

When I've set XFRLEN1 and RFRLEN1 = 8 all is fine - I have all my data in one packet. But is this safe to run on production? If there be modification in some core version where this "hack" isn't working?

Some of TI man can ansfer?

I'm using DMA for transferring data thru Mcbspa in SPI Clock Stop Mode.

  • 0
    Guru 30330 points
    Lukas,

    I Split this thread from: e2e.ti.com/.../99655 Please try to create new posts where you include a link to the original thread.

    To answer your questions, The design mandates that the XFRLEN1 and RFRLEN1 are set to 1. While you may see that it is working sometimes, we cannot guarantee that the design will operate properly under all conditions.

    As a workaround, you may choose to not use the McBSP FSX signal and instead use a manually controlled GPIO which toggles at the proper time.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Guru 30330 points
    Lukas,

    Can you share your McBSP configuration code? I have put this question into our design team for analysis. It would be great if we can try to reproduce how this seems to be working as expected for you.

    Thanks!
    Mark
  • 0 in reply to Mark Labbato
    Intellectual 335 points
    Hello,

    after more testing - this is'nt worked for me. I have problems with random unsynchronization after about 4 words of data transmission. Sometimes is synchronized - sometimes isn't. I've changed to single burst and it is ok now.

    So i think it is problem with synchronization on receiving data.
  • 0 in reply to Lukas Brzyszkiewicz
    Guru 30330 points
    Lukas,

    If you can share your configuration code, we can confirm the behavior you are seeing here.

    What appears to happen is that on the first word of the transmission, the correct 8 bits are transferred, the second word will generate 10 bits, throwing off the synchronization and every second word will be incorrect.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Intellectual 335 points
    Hi,

    We are currently changing DSC in our project to F28377 and moved signal lines from McBSP to SPI so this problem is irrelevant.
    Thank you very much for your assistance.

    Łukasz.