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When the CLA is set up so that an interrupt, say EPWM1INT, triggers a particular CLA task to execute, is it possible that EPWM1INT to the CLA will be delayed, and hence delay the execution of the task, by a higher priority interrupt that's handled by CPU1?
I don't see this happening in my application, but the thought just occurred to me that this would be a problem if it were true. If you know of somewhere in the technical reference manual that this is addressed, please let me know... Thanks!
