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TMS320F280049M: ADC Sampling to Conversion Time

Kengo Furuya
Expert 7650 points

Part Number: TMS320F280049M

Hello Team,

I want reduce the Sampling to Conversion time of ADC as much as possible. So please answer to the following questions.

1. In 5.9.1.2 ADC Electrical Data and Timing, Sample window duration (set by ACQPS and PERx.SYSCLK) is described as 75ns(Min). So, in case of Sysclk 100MHz, is 80ns min value with ACQPS = 7? 

2. I'm checking In 5.9.1.2.2 ADC Timing Diagram, and understanding the conversion time will be 310ns (tSH + tLAT = 80ns＋230ns）at ACQPS = 7 and ADCCLK50MHz. Is it correct?

3. If any idea to reduce the sampling to conversion time, please let me know.

Regards,

Furuya 

  • 0
    TI__Mastermind 34785 points

    Hi Furuya,

    For question #1, yes you are correct the minimum sample window is 80ns for a SYSCLK of 100MHz [(7+1)*10nS = 80ns].  For question #2, the total conversion time for one SOC would be 310ns when SYSCLK is 100MHz and ADCCLK is 50MHz.

    Unfortunately, conversion time for one SOC will be limited to sampling time and latency (tSH+tLAT). tLAT is fixed and it is not recommended to go below the tSH as accuracy will not be guaranteed below the minimum required sampling window.  What you can possibly do is oversample a channel using another SOC to initiate a conversion in the tLAT region.  For example, you want to convert on channel 0.  You can configure several SOCs and assign them all to channel 0 and trigger the SOCs through ePWMs.  You can time the ePWM triggers such that they will occur after an SOC tSH expires while waiting on tLAT.  You can do this with several SOCs.

    Regards,

    Joseph