Part Number: TMS320F28377D
Other Parts Discussed in Thread: CONTROLSUITE
Hi,
a customer is setting up the SPI and DMA to access an MRAM device. https://www.everspin.com/family/mr25h10
The setup is like the example in the ControlSuite
C:\TI\controlSUITE\device_support\F2837xD\v200\F2837xD_examples_Cpu1\spi_loopback_dma\cpu01\Example_2837xD_Spi_dma.c
The problem is that on both TX and RX side the transfers are not going through reliably. For example when setting the RX and TX FIFO level to 4, the customer can write and read 8 bytes successfully, but not more, the rest of the data is not correct. When setting the FIFO level to a higher number like 10, more data can be written/read, but less than 15 bytes are useful data.
There is code to setup the RX and TX FIFO in the example
SpiaRegs.SPIFFRX.all=0x2040; // RX FIFO enabled, clear FIFO int
SpiaRegs.SPIFFRX.bit.RXFFIL = FIFO_LVL; // Set RX FIFO level
SpiaRegs.SPIFFTX.all=0xE040; // FIFOs enabled, TX FIFO released,
SpiaRegs.SPIFFTX.bit.TXFFIL = FIFO_LVL; // Set TX FIFO level
The DMA transfers are setup with BURST_LENGTH equal to the RX and TX FIFO level. This is done based on TRM chapter 18.3.8.1 Transmitting Data Using SPI with DMA and 18.3.8.2 Receiving Data Using SPI with DMA.
Have you seen this kind of behavior with SPI and DMA?
Thanks,
--Gunter
