Hi Team,
My customer has some question about out HVPSFB design, could you help on these question:
There have three SR mode, what is the advantage or disadvantage between SR mode1 and SR mode2?
In VMC mode EPWM initial code ,why PWM1 TBPRD = period, PWM2 TBPRD = period-1 and PWM4 CMPA= period/2 – 6.
Why for SR PWM the TBPRD is load Immediate but the CMPA use shadow mode.
What is the advantage or disadvantage between PCMC and VMC mode
Hi Huihuang,
Please see my answers below:
1. This has been answered in section 2.4 of the following document.
2. This is done to make sure the phase syncing between the master PWM (PWM1) and the slave PWMs works well. A smaller period value for the slave PWM ensures that the slave PWM counter will count to a value of 0 allowing the new phase and duty (compare) values to be correctly updated for the next cycle.
3. As this is a fixed frequency converter, the period loading can be immediate. However, as the duty (CMP) value changes for SR PWM, the compare registers use shadow loading for proper operation.
4. This has been covered in detail in many IEEE papers but, in brief, PCMC is the preferred scheme because it provides cycle by cycle current limiting, flux balancing without a need for DC blocking capacitors, and is in general easier to tune. PCMC requires slope compensation and is, in general, more difficult to implement. VMC on the other hand is much easier to implement.
I hope this helps.
Hrishi
