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TMS320F28379D: TMS320F28379D ADC offset problem

Alican Madan
Intellectual 255 points
Part Number: TMS320F28379D
Other Parts Discussed in Thread: TIDM-HV-1PH-DCAC

   Hello everyone,
I am currently using  F28379D Delfino in a single phase inverter. Inverter is TIDM-HV-1PH-DCAC experiment kit. I have a problem while sensing output voltage via ADC module on the DSP. Output Voltage comes with an offset when inverter is under operation. On the other hand, when inverter is disabled, i am applying sine wave directly to the output from an external power supply. In this case ADC measurment is fine. I thought measurment offset comes from switching noise and make filtration on the hardware. But the problem is still valid. My question is that is there any way to overcome this offset error via software? ADC offset calibration seems like a hardware mathematical differantiation for ADC input. Is this a common problem or not? Thanks 

   Regards
   Alican Madan

  • 0
    TI__Guru 60865 points
    HI Alican,

    How many LSBs is the offset error you observe? What circuitry do you use for signal conditioning to get the output voltage scaled into the range of the ADC input? When you drive in the voltage from the power-supply and get good results, is this directly into the ADC pin or is this into the output bus which then goes through the same signal conditioning circuitry as normal operation? How long is the S+H duration for the channel in question (set by the ACQPS field)? Do you observe this offset error on all the ADC channels, or just the one output voltage signal?
  • 0 in reply to Devin Cottier
    Intellectual 255 points
    Hi Devin,

    I am using the same voltage sense circuit in TIDM-HV-1PH-DCAC experiment kit. Also I sense power supply output from output bus which goes through the same signal conditioning circuitry. S+H duration is 101 system clock cycle (AdcaRegs.ADCSOC0CTL.bit.ACQPS=100). Also I have tried it with different sample and hold durations. I only observed this offset problem in the voltage sense. The only difference from experiment kit is that I have changed sinusoidal PWM technique in the experiment kit. In the experiment's kit one leg of the full bridge inverter is switching with 20 kHz and other leg is switching with 50 Hz. In my switching technique, two legs are switching with 20 kHz with Unipolar PWM. Actually I did not measure offset by means of LSB. Because the difference between expected register value and measured have a non linear characteristic. Can it be due to switching noise or layout problem?

    Regards
  • 0 in reply to Alican Madan
    TI__Mastermind 43730 points
    Alican,

    What is the measure of the offset ? are you checking the Vrms value of the output ?

    Vrms calculation can have some errors, specially because of the additional noise when the inverter is operating and might vary .. this might not happen when you feed a clean AC input at the output.
  • 0 in reply to Manish Bhardwaj
    Intellectual 255 points
    Hi Manish,

    Actually I have plotted the output voltage from data taken from each interrupt. Output Voltage has a mean value which has a non linear characteristic. Therefore; displayed output voltage has an offset. The difference between measured value from scope and displayed value are increasing when the switching instant of two legs are getting closer to each other. This situation actually makes me think about switching noise problem. Offset has -8 V average value @ 50 Hz 220 Volt RMS.
  • 0 in reply to Alican Madan
    TI__Mastermind 43730 points
    Alican,

    I would suggest the following

    1. probing the voltage feedback with the oscilloscope using a differential probe, you may need to solder a wire on the board. Check if you see the same offset on the oscilloscope.

    2. Are you checking this at build level 3? the hall effect current sensor current offset can also play a role if it is build level 3. I would suggest doing the tests at build level 1 to eliminate other potential issues related to control scheme and other sensors.

    8V will be around 1.7% offset which seems high to me ..