Part Number: TMS320F28075
Hi,
I made some tests with IF3 registers of CAN B module and I have some questions about it.
I configured message object 2 as reiceve mailbox and I enabled automatic IF3 update in IF3UPD register.
Moreover I enabled receive interrupt linked to mailbox 2 on INT0 line.
1) CAN_INT REGISTER = 0
When a message has been stored in receive mailbox 2 the interrupt routine is called but the registers have the following values:
CAN_ES = 0x00000010 -> RxOk: expected value
CAN_INT = 0 -> No interupt pending: not expected!
CAN_IPEN_X = 0 -> No interupt pending: not expected!
CAN_IPEN_21 = 0 -> No interupt pending: not expected!
Therefore inside an interrupt routine I cannot identify the cause of the interrupt.
I presume that CAN_INT, CAN_IPEN_X andh CAN_IPEN_21 have 0 value because automatic data transfer from mailbox 2 to IF3 registers reset bit IntPnd (see also e2e.ti.com/.../2140585
Is there any way to know which is the cause of the interrupt?
2) IF3 TRANSFER COMPLETION
When the receive interrupt routine is issued, has the automatic data transfer from the mailbox to IF3 registers been completed?
If not, how can I know when the transfer has been completed?
3) IF3 REPETITIVE READING
Consider the following scenario:
1. message 1 has been stored in receive mailbox 2;
2. message 1 is automatically transferred to IF3 registers;
3. the interrupt routine is issued and begins to be served (IF3 registers have not been read read till now, so IF3Upd bit = 1);
4. message 2 has been stored in receive mailbox 2 before IF3 registers have been read, so message 2 isn't transferred to IF3 registers;
5. during interrupt routine IF3 registers are read so IF3Upd bit goes to 0;
6. now message 2 is transferred from mailbox 2 to IF3 registers so IF3Upd bit goes to 1 again;
7. because IF3Upd bit is = 1 IF3 registers are read so IF3Upd bit goes (and stay) to 0;
8. the interrupt routine ends.
In step 7 IF3Upd bit is tested to check if there is another message to read. However IF3 registers set doesn't have a Busy bit like IF1/2 registers so I don't know if a transfer from mailbox to IF3 register is in progress.
During my tests I noted these fatcs:
- if I read IF3 registers and soon after I test IF3Upd bit I will find it equal to 0 even if there's another message in mailbox, because the transfer is in progress;
- if I read IF3 registers and soon after I test IF3Upd bit 3-4 times (empirical) I will find it equal to 1 if there's another message in mailbox, because during the repetitive tests the transfer to IF3 registers has been completed.
Which is the right sequence to test IF3Upd bit?
How many times should I test it after reading IF3 registers?
Or better, how much time should I wait before test IF3Upd bit after reading IF3 registers?
Thank you.
Best regards,
Demis
