Part Number: TMS320F2812
I am trying to use pins /C4TRIP and /C5TRIP to trigger a PDPINTB when either signal goes low. The new board that I have breaks with convention in our company and uses the /TC3TRIP_PDPINTB and /TC1TRIP_PDPINTA as GPIO. I am experiencing an unexpected PDPINTB interrupt after initialization. I have a breakpoint set in my ISR and EvbRegs.EVBIFRA.bit.PDPINTB=0 for this interrupt. All future legitimate interrupts have EvbRegs.EVBIFRA.bit.PDPINTB=1. I have verified in that unexpected interrupt that C1TRIPE, C2TRIPE, C3TRIPE, C6TRIPE, T1CTRIPE, T2CTRIPE, T3CTRIPE, and T4CTRIPE are all zero, Besides C4TRIPE and C5TRIPE which should be 1 and since /TC3TRIP_PDPINTB is GPIO, are there any other sources for this interrupt?
Here is my initialization code:
// **********************************************************************************
// Name: InitC4C5Trip
// Description: Setup C4Trip and C5Trip
// Parameters: none
// **********************************************************************************
#pragma CODE_SECTION (InitC4C5Trip, "ramfuncs")
void InitC4C5Trip(void)
{
// ------------------------------------------------------------------------------
// Enable C4TRIP and C5TRIP interrupts
// ------------------------------------------------------------------------------
EALLOW;
GpioMuxRegs.GPBMUX.bit.C4TRIP_GPIOB13 = 1; // use as peripheral
GpioMuxRegs.GPBMUX.bit.C5TRIP_GPIOB14 = 1; // use as peripheral
EDIS;
// ------------------------------------------------------------------------------
// C4C5Trip_IRQ interrupt setup
// ------------------------------------------------------------------------------
EALLOW;
PieVectTable.PDPINTB = &PDP_B_IRQ;
PieVectTable.PDPINTA = &PDP_A_IRQ;
EDIS;
IER |= M_INT1;
// ------------------------------------------------------------------------------
// PDPINT setup interrupt mask & flag
// ------------------------------------------------------------------------------
EvbRegs.EXTCONB.bit.INDCOE = 1;
EvaRegs.COMCONA.bit.C1TRIPE = 0;
EvaRegs.COMCONA.bit.C2TRIPE = 0;
EvaRegs.COMCONA.bit.C3TRIPE = 0;
EvaRegs.GPTCONA.bit.T1CTRIPE = 0;
EvaRegs.GPTCONA.bit.T2CTRIPE = 0;
EvbRegs.COMCONB.bit.C4TRIPE = 1;
EvbRegs.COMCONB.bit.C5TRIPE = 1;
EvbRegs.COMCONB.bit.C6TRIPE = 0;
EvbRegs.GPTCONB.bit.T3CTRIPE = 0;
EvbRegs.GPTCONB.bit.T4CTRIPE = 0;
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; // PDPINTB
// -------------------------------------
// PDPINT setup interrupt mask & flag
// -------------------------------------
EvbRegs.EVBIFRA.bit.PDPINTB = 1; // PDPINTB, IRQ flag reg., reset interrupt flag
EvbRegs.EVBIMRA.bit.PDPINTB = 1; // PDPINTB, IRQ mask reg., enable interrupt
}
Errata SPRZ193N section 4.1.1 mentions:
"Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state that can trigger an unwanted interrupt. The conditions required to enter this state are:
1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
2. A nested interrupt clears one or more PIEIER bits for its group."
However, I do not believe that I have this situation. Has anyone else seen this issue and hopefully, resolved it?
If I can't get this resolved I think my potential workaround is to go back to my hardware engineer and have him run /C4TRIP and /C5TRIP pins through an OR gate to /T1CTRIP_PDPINTA and use /C4TRIP and /C5TRIP as GPIO.
