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TMS320F28375S: Power up and VREFHI

Part Number: TMS320F28375S
Other Parts Discussed in Thread: OPA350

Team,

My customer has the following questions related to the TMS320F28375S.

How soon after 3.3V is applied must 1.2V be applied? I’m assuming it’s indefinite.

 

Why are the buffers needed for the VREFHI inputs? If using the 16 bit mode, each VREFHI requires a 22µF capacitor which seems like a lot for an op amp and then you lose some benefit by inserting some series resistance to prevent instability. The tech reference suggests the REF5025 whose datasheet says to use a 1 – 50 µF capacitor for best stability. I would think this could drive two 22µF capacitors just fine (?). Would you also recommend a lower-value, parallel cap as well (0.1µF)? Do I understand correctly that 16-bit mode must have a fed a differential signal (and you can’t fake it out by tied ADCIN_N to VSSA)?

 

The LAUNCHXL schematic has filtered power for VDDOSC, VDDA, VDDIO, and VDD3VFL tied directly to 3.3V. Why was this done and do you have any guidance for a filter design for these power supply inputs? Am I OK with just tying them all to +3.3V? +3.3V will be used for other components (some linear/analog circuits, some digital) in the system.

Thanks,

Aaron

  • Hi Aaron,

    We specify a minimum power supply ramp rate of 330V/s in datasheet section 5.7.1 "Power Sequencing". Based on this, the 1.2V rail should power-up in no more than 3.63ms

    ADC reference inputs draw pretty sharp transient currents as the ADC converts. The reference pin voltage also needs to settle back to well within the ADC resolution during each ADCCLK. Because of this, you typically need both a large capacitor on the ADC input and a high-bandwidth driver to get the best possible performance out of the ADC. The REF50xx parts have great accuracy and can drive the large capacitor, but don't have the speed for directly driving the ADC reference. This is why we require an op-amp to drive the ADC reference. Based on characterization results, if you want to use 16-bit mode your best choice for a driver is OPA350 + 22uF capacitor w/ a 0.100 ohm snubbing resistor to ensure stability. This circuit can drive 2 VREFHI inputs. Adding a smaller parallel capacitor to the VREFHI input pin would also probably help, but our characterization shows that the single large cap, very close to and directly across the VREFHI to VREFLO pins is sufficient.

    For the various 3.3V rails, it is fine if you source these all from the same LDO, DC-DC, or other power supply. You can also hang other ICs on the PCB off of this same rail. The most important thing is to ensure the power-supply can supply the maximum instantaneous current draw and that each pin of each device on the rail is decoupled with its own decoupling capacitor placed very close to the pin. Good layout, routing, and board stack-up are also important. If you do everything else well, inductive filters for each supply pin shouldn't be necessary, but you can always add these if desired.