Other Parts Discussed in Thread: OPA350
Team,
My customer has the following questions related to the TMS320F28375S.
How soon after 3.3V is applied must 1.2V be applied? I’m assuming it’s indefinite.
Why are the buffers needed for the VREFHI inputs? If using the 16 bit mode, each VREFHI requires a 22µF capacitor which seems like a lot for an op amp and then you lose some benefit by inserting some series resistance to prevent instability. The tech reference suggests the REF5025 whose datasheet says to use a 1 – 50 µF capacitor for best stability. I would think this could drive two 22µF capacitors just fine (?). Would you also recommend a lower-value, parallel cap as well (0.1µF)? Do I understand correctly that 16-bit mode must have a fed a differential signal (and you can’t fake it out by tied ADCIN_N to VSSA)?
The LAUNCHXL schematic has filtered power for VDDOSC, VDDA, VDDIO, and VDD3VFL tied directly to 3.3V. Why was this done and do you have any guidance for a filter design for these power supply inputs? Am I OK with just tying them all to +3.3V? +3.3V will be used for other components (some linear/analog circuits, some digital) in the system.
Thanks,
Aaron