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TMS320F28379D: DMA and CPU access behavior to Global Shared (GS) RAM

BrandonAzbell
Guru 63850 points
Part Number: TMS320F28379D

I would like to clarify behavior of the TMS320F28379D device when both the CPU and the DMA engine are accessing Global Shared (GS) RAM.

Section 4.4 of the Technical Reference Manual, it indicates that the CPU access will stall until the DMA completes an access the same memory interface.  Specifically, the caption is :

"In the case of a block DMA transfer to and from the same memory interface the CPU is trying to access, the arbitration will stall CPU access until the DMA completes an access, not the entire transfer."

I would like to clarify if this means that a CPU access will stall if both the CPU and DMA are accessing any memory segment within the GS RAM space?  Or is there more granularity such that a stall happens only if both the CPU and DMA are accessing the same memory segment (eg. GS1)?

Thank you.

  • 0
    TI__Guru** 113745 points

    Hi Brandon,

    I would like to clarify if this means that a CPU access will stall if both the CPU and DMA are accessing any memory segment within the GS RAM space?  Or is there more granularity such that a stall happens only if both the CPU and DMA are accessing the same memory segment (eg. GS1)?

    Stall only happens when both CPU and DMA are accessing the same memory segment/block. DMA and CPU can access two different GSx RAM block at same time without any stall.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru 63850 points
    Thank you, Vivek. I appreciate the clarity. That is what I had thought, but didn't want to assume anything.

    I would like to formally suggest that if there is a revision to the Technical Reference Manual opportunity, it would be beneficial to provide this clarity in the document.
  • 0 in reply to BrandonAzbell
    TI__Guru** 113745 points
    Thank you for the feedback Brandon. We have taken note of this and will try to update the detail in next revision of document to clarify the same.

    Regards,
    Vivek Singh
  • 0 in reply to Vivek Singh
    TI__Guru** 113745 points
    Also more details about access arbitration for shared RAMs are provided in section "2.11.1.6 Access Arbitration" (in Memory Controller Module chapter) of TRM.

    Vivek Singh